Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,961,127 Variable gain stage having same input capacitance regardless of the stage gain
A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes...
US-7,961,019 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
US-7,960,988 Contactor for electrical test, electrical connecting apparatus using the same, and method for manufacturing...
An electrical test contactor comprises a contactor main body including a plate-shaped attachment portion extending in the up-down direction, a plate-shaped arm...
US-7,960,829 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the...
US-7,960,813 Programmable resistance memory devices and systems using the same and methods of forming the same
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first...
US-7,960,803 Electronic device having a hafnium nitride and hafnium oxide film
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,960,797 Semiconductor devices including fine pitch arrays with staggered contacts
A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one...
US-7,960,291 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
US-7,959,975 Methods of patterning a substrate
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-7,958,491 Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
US-7,958,439 Defective memory block remapping method and system, and memory device and processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an...
US-7,957,215 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable...
US-7,957,214 Adjustable voltage regulator for providing a regulated output voltage
Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator...
US-7,957,206 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
US-7,957,198 Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory...
US-7,957,196 Method of programming memory cells of series strings of memory cells
Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after...
US-7,957,182 Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same
A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes...
US-7,957,055 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a...
US-7,956,914 Imager methods, apparatuses, and systems providing a skip mode with a wide dynamic range operation
Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an...
US-7,956,912 Active pixel sensor with mixed analog and digital signal integration
An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,...
US-7,956,685 Adaptive operational transconductance amplifier load compensation
A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The...
US-7,956,673 Variable stage charge pump and method for providing boosted output voltage
An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage....
US-7,956,648 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-7,956,443 Through-wafer interconnects for photoimager and memory wafers
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making...
US-7,956,426 Lanthanide dielectric with controlled interfaces
Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer...
US-7,956,416 Integrated circuitry
Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material...
US-7,956,402 Double-doped polysilicon floating gate
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method...
US-7,955,976 Methods of forming semiconductor structures
The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an...
US-7,955,946 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit,...
The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a...
US-7,955,935 Non-volatile memory cell devices and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots,...
US-7,955,917 Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are...
US-7,955,898 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
US-7,955,836 Microfluidic mixing and analytical apparatus
Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles...
US-7,955,764 Methods to make sidewall light shields for color filter array
Methods of forming color filters having a light blocking material therebetween. A color filter is formed such that a trench is defined between a color filter...
US-7,954,029 System, apparatus, and method for memory built-in self testing using microcode sequencers
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions...
US-7,954,004 Systems and methods for retrieving data
Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques...
US-7,953,954 Flash storage partial page caching
Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device...
US-7,953,579 Jittery signal generation with discrete-time filtering
The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the...
US-7,952,952 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,952,936 Program-verify method
Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory...
US-7,952,927 Adjusting program and erase voltages in a memory device
A method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. A method...
US-7,952,924 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
US-7,952,922 Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect
A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data....
US-7,952,919 Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
US-7,952,913 Back gated SRAM cell
One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a...
US-7,952,631 CMOS imager with integrated circuitry
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS...
US-7,952,184 Distributed semiconductor device methods, apparatus, and systems
Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be...
US-7,952,174 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is...
US-7,952,171 Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a...
US-7,952,170 System including semiconductor components having through interconnects and back side redistribution conductors
A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.