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Patent # Description
US-7,936,637 System and method for synchronizing asynchronous signals without external clock
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an...
US-7,936,610 Selective refresh of single bit memory cells
Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans...
US-7,936,608 Memory device operation
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines...
US-7,936,606 Compensation of back pattern effect in a memory device
In one or more of provided embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases...
US-7,936,599 Coarse and fine programming in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,936,203 Temperature compensation via power supply modification to produce a temperature-independent delay in an...
A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated...
US-7,936,199 Apparatus and method for external to internal clock generation
A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first...
US-7,936,058 Stacked package and method for forming stacked package
The present invention provides an inexpensive semiconductor chip module enabling sufficient heat dissipation without complicating the manufacture process. A...
US-7,936,000 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,935,999 Memory device
A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are...
US-7,935,997 Low resistance peripheral contacts while maintaining DRAM array integrity
An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM...
US-7,935,991 Semiconductor components with conductive interconnects
A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a...
US-7,935,639 Process for increasing feature density during the manufacture of a semiconductor device
Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each...
US-7,935,633 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,935,618 Sputtering-less ultra-low energy ion implantation
Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering...
US-7,935,610 Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a...
US-7,935,602 Semiconductor processing methods
The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the...
US-7,935,242 Method of selectively removing conductive material
An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising...
US-7,934,945 Electrical connecting apparatus
An embodiment of an electrical connecting apparatus comprises a support board, a plate spring arranged on the support board, an attachment device attaching the...
US-7,934,944 Electrical connecting apparatus
An embodiment of an electrical connecting apparatus comprises a support board having an upper surface and a lower surface, a block having an attachment surface...
US-7,934,172 SLM lithography: printing to below K1=.30 without previous OPC processing
Previously disclosed methods and devices are extended in this application by two-dimensional analysis of optical proximity interactions and by fashioning a...
US-7,934,048 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-7,933,761 Creation of clock and data simulation vectors with periodic jitter
Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal...
US-7,933,162 Row addressing
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a...
US-7,933,142 Semiconductor memory cell and array using punch-through to program and read same
An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the...
US-7,933,140 Techniques for reducing a voltage swing
Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a...
US-7,932,938 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-7,932,875 Microdisplay and interface on a single chip
A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same...
US-7,932,557 Semiconductor contact device
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and...
US-7,932,550 Method of forming high aspect ratio structures
An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure...
US-7,932,179 Method for fabricating semiconductor device having backside redistribution layers
Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment...
US-7,932,174 Method of making a semiconductor device having improved contacts
A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole....
US-7,932,173 Method of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed...
US-7,932,003 Methods of forming and using reticles
Some embodiments include methods of treating reticles to provide backside masking across regions of the reticle to compensate for problems occurring during...
US-7,931,769 Method of forming temporary carrier structure and associated release techniques
A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to...
US-7,930,657 Methods of forming photomasks
Some embodiments include methods in which a mathematical representation of a photomask construction is defined, with such representation comprising a plurality...
US-7,930,653 Triangulating design data and encoding design intent for microlithographic printing
The present disclosure relates to fracturing of polygon data, with one application being microlithography. In particular, it relates to preserving data...
US-7,930,612 Error detection and correction scheme for a memory device
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are...
US-7,930,518 Method for manipulating data in a group of processing elements to perform a reflection of the data
A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until...
US-7,929,798 Method and apparatus providing noise reduction while preserving edges for imagers
A method of reducing noise in an image including steps for obtaining a first value for a target pixel, obtaining a respective second value for each neighboring...
US-7,929,368 Variable memory refresh devices and methods
Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples...
US-7,929,343 Methods, devices, and systems relating to memory cells having a floating body
Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a...
US-7,929,329 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-7,928,782 Digital locked loops and methods with configurable operating parameters
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or...
US-7,928,781 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-7,928,710 Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Devices, reference voltage generators, systems and methods may include an embodiment of a voltage regulator output transistor using a thin gate insulator to...
US-7,928,582 Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic...
US-7,928,579 Devices including sloped vias in a substrate and devices including spring-like deflecting contacts
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed...
US-7,928,577 Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the...
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-7,928,503 Memory cells
Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are...
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