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Patent # Description
US-7,989,866 DRAM layout with vertical FETS and method of formation
DRAM cell arrays having a cell area of about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,989,864 Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from...
US-7,989,362 Hafnium lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of...
US-7,989,360 Semiconductor processing methods, and methods for forming silicon dioxide
Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate...
US-7,989,349 Methods of manufacturing nanotubes having controlled characteristics
A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further,...
US-7,989,345 Methods of forming blind wafer interconnects, and related structures and assemblies
Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface...
US-7,989,340 Methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive...
The invention included to methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts. In one...
US-7,989,336 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of...
A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a...
US-7,989,322 Methods of forming transistors
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,989,311 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,989,307 Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and...
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography...
US-7,989,290 Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic...
US-7,989,288 Transistor constructions and processing methods
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second...
US-7,989,285 Method of forming a film containing dysprosium oxide and hafnium oxide using atomic layer deposition
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a...
US-7,989,251 Variable resistance memory device having reduced bottom contact area and method of forming the same
A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom...
US-7,989,022 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and...
A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to...
US-7,988,529 Methods and tools for controlling the removal of material from microfeature workpieces
Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method...
US-7,986,578 Low voltage sense amplifier and sensing method
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the...
US-7,986,576 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,986,563 NAND flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a...
US-7,986,555 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain...
US-7,986,553 Programming of a solid state memory utilizing analog communication of bit patterns
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,986,549 Apparatus and method for refreshing or toggling a phase-change memory cell
An apparatus and a method for refreshing or toggling a phase-change memory cell are described. The apparatus includes a voltage ramp element coupled to the...
US-7,986,363 High dynamic range imager with a rolling shutter
A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the...
US-7,985,995 Zr-substituted BaTiO.sub.3 films
The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO.sub.3), produces a reliable ferroelectric...
US-7,985,698 Methods of forming patterned photoresist layers over semiconductor substrates
This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is...
US-7,985,692 Method to reduce charge buildup during high aspect ratio contact etch
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide...
US-7,985,681 Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during...
A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or...
US-7,985,679 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-7,985,617 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-7,983,516 Zinc oxide diodes for optical interconnections
The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined...
US-7,983,108 Row mask addressing
Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional...
US-7,983,090 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,983,088 Programming in a memory device
Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is...
US-7,983,085 Memory array with inverted data-line pairs
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory...
US-7,983,070 DRAM tunneling access transistor
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side...
US-7,982,494 Systems and methods for detecting terminal state and setting output driver impedance
Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to...
US-7,982,255 Flash memory with recessed floating gate
A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a...
US-7,981,736 Systems and devices including multi-gate transistors and methods of using, making, and operating the same
Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and...
US-7,981,303 Method of manufacturing monocrystalline silicon micromirrors
A novel silicon micromirror structure for improving image fidelity in laser pattern generators is presented. In some embodiments, the micromirror is formed from...
US-7,981,221 Rheological fluids for particle removal
Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and...
US-7,979,757 Method and apparatus for testing high capacity/high bandwidth memory devices
A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are...
US-7,978,721 Multi-serial interface stacked-die memory architecture
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding...
US-7,978,556 On-chip temperature sensor
A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant...
US-7,978,529 Rewritable single-bit-per-cell flash memory
Subject matter disclosed herein relates to multilevel flash memory, and more particularly to a method of changing a logic level of a single-bit-per-cell flash...
US-7,978,511 Data line management in a memory device
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device...
US-7,978,500 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive...
US-7,978,491 Stacked memory cell structure and method of forming such a structure
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell...
US-7,978,411 Tetraform microlenses and method of forming the same
A lens is formed to support and tilt at least one microlens formed on the lens. The degree and direction of slope of the microlens can be controlled based on...
US-7,978,000 Semiconductor temperature sensor using bandgap generator circuit
A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators...
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