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Memory system and method having volatile and non-volatile memory devices
at same hierarchical level
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer...
Methods for programming a memory device and memory devices using inhibit
voltages that are less than a supply...
Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less...
Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
Memory cell operation
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of...
Programming based on controller performance requirements
Methods and solid state drives are disclosed, including a solid state drive that is adapted to receive and transmit analog data signals representative of bit...
Lens master devices, lens structures, imaging devices, and methods and
apparatuses of making the same
A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a...
Multiple microlens system for image sensors or display
An imager or display system with multiple lenses, which are formed, patterned and shaped over one or more pixels in an imager or display array. The multiple...
Anti-eclipse circuitry with tracking of floating diffusion reset level
An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent...
Circuitry and methods for improving differential signals that cross power
Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain...
Method and apparatus for selecting an operating mode based on a
determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
Antifuse programming circuit with snapback select transistor
An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The...
Microfeature workpieces and methods for forming interconnects in
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a...
Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
Interconnecting substrates for microelectronic dies, methods for forming
vias in such substrates, and methods...
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed...
Apparatus for flip-chip packaging providing testing capability
A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating...
Semiconductor assemblies and methods of manufacturing such assemblies
including trenches in a molding material...
Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of...
Semiconductor structure including gateline surrounding source and drain
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
Devices with cavity-defined gates and methods of making the same
A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a...
Dielectric stack containing lanthanum and hafnium
Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in...
Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
Methods of forming non-volatile memory cells, and methods of forming NAND
cell unit string gates
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
Relaxed-pitch method of aligning active area to digit line
According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at...
Methods of making metal core foldover package structures
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked ...
Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
Method and apparatus for address FIFO for high bandwidth command/address
busses in digital storage system
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a...
Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The...
Method for measuring the position of a mark in a deflector system
The present invention relates to a method for determining the coordinates of an arbitrarily shaped pattern in a deflector system. The method basically comprises...
Column/row redundancy architecture using latches programmed from a look up
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
Temperature compensation of memory signals using digital signals
A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates...
Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
Apparatus and methods for a physical layout of simultaneously
sub-accessible memory modules
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of...
Multi-phase signal generator and method
A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals...
Memory array with ultra-thin etched pillar surround gate access
transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
Methods of forming vertical field effect transistors, vertical field
effect transistors, and dram cells
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the...
Self-aligned, planar phase change memory elements and devices
Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second...
Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
Reverse masking profile improvements in high aspect ratio etch
A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of...
Trim process for critical dimension control for integrated circuits
Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of...
Pixel and imager device having high-k dielectrics in isolation structures
An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention...
Small electrode for resistance variable devices
A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a...
Method of fabricating microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a...
Mask material conversion
The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form...
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
Memory command delay balancing in a daisy-chained memory topology
A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the...
High speed, wide frequency-range, digital phase mixer and methods of
The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output...
Memory device having data paths permitting array/port consolidation and
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads...
Memory device reference cell programming method and apparatus
Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example,...
Package structure for multiple die stack
A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first...