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Patent # Description
US-7,929,798 Method and apparatus providing noise reduction while preserving edges for imagers
A method of reducing noise in an image including steps for obtaining a first value for a target pixel, obtaining a respective second value for each neighboring...
US-7,929,368 Variable memory refresh devices and methods
Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples...
US-7,929,343 Methods, devices, and systems relating to memory cells having a floating body
Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a...
US-7,929,329 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-7,928,782 Digital locked loops and methods with configurable operating parameters
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or...
US-7,928,781 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-7,928,710 Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Devices, reference voltage generators, systems and methods may include an embodiment of a voltage regulator output transistor using a thin gate insulator to...
US-7,928,582 Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic...
US-7,928,579 Devices including sloped vias in a substrate and devices including spring-like deflecting contacts
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed...
US-7,928,577 Interconnect structures for integration of multi-layered integrated circuit devices and methods for forming the...
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of...
US-7,928,503 Memory cells
Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are...
US-7,928,019 Semiconductor processing
Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor...
US-7,927,996 Tungsten-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain...
US-7,927,975 Semiconductor material manufacture
Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can...
US-7,927,964 Methods of forming electrically insulative materials, methods of forming low k dielectric regions, and methods...
Some embodiments include methods of forming low k dielectric regions between electrically conductive lines. A construction may be formed to have a plurality of...
US-7,927,948 Devices with nanocrystals and methods of formation
An aspect relates to a method of growing nanoscale structures on a semiconductor substrate. According to various embodiments, nucleation sites are created on a...
US-7,927,938 Fin-JFET
Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate...
US-7,927,923 Method and apparatus for directing molding compound flow and resulting semiconductor device packages
Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding...
US-7,927,916 Optic wafer with reliefs, wafer assembly including same and methods of dicing wafer assembly
An optic wafer for assembly with an imager wafer, the optic wafer comprising a plurality of reliefs in a surface thereof coincident with street locations...
US-7,927,500 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,927,181 Apparatus for removing material from microfeature workpieces
Machines and systems for removing materials from microfeature workpieces using fixed-abrasive mediums. One embodiment of a method for removing material from a...
US-7,925,949 Embedded processor
Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a...
US-7,925,910 Systems, methods and devices for limiting current consumption upon power-up
Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each...
US-7,925,844 Memory register encoding systems and methods
Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to...
US-7,924,630 Techniques for simultaneously driving a plurality of source lines
Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an...
US-7,924,623 Method for memory cell erasure with a programming monitor of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase...
US-7,924,619 Programming method to reduce word line to word line breakdown for NAND flash
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of...
US-7,924,617 Selective threshold voltage verification and compaction
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of...
US-7,924,616 Word line voltage boost system and method for non-volatile memory devices and memory devices and...
The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by...
US-7,924,603 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb.sub.2Se.sub.3, and...
US-7,924,337 Dual panel pixel readout in an imager
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual...
US-7,924,038 Probe and electrical connecting apparatus using it
A probe having an alignment mark that is hardly influenced by scraps of an electrode scraped by a probe tip is provided. A probe according to the present...
US-7,924,034 Electric connecting apparatus
In an electrical connecting apparatus, a thermal deformation restriction member, a reinforcing plate, and an auxiliary member are made of materials having...
US-7,923,824 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,923,381 Methods of forming electronic devices containing Zr-Sn-Ti-O films
A dielectric film containing Zr--Sn--Ti--O and methods of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide...
US-7,923,373 Pitch multiplication using self-assembling materials
Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed...
US-7,923,364 Tunnel dielectric comprising nitrogen for use with a semiconductor device and a process for forming the device
A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS...
US-7,923,322 Method of forming a capacitor
A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed...
US-7,923,308 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local...
US-7,923,298 Imager die package and methods of packaging an imager die on a temporary carrier
Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication...
US-7,923,182 Multi-focus method of enhanced three-dimensional exposure of resist
The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a...
US-7,923,181 Methods of forming photomasks
Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to...
US-7,923,070 Atomic layer deposition method of forming conductive metal nitride-comprising layers
This invention includes atomic layer deposition methods of forming conductive metal nitride comprising layers. In one implementation, an atomic layer deposition...
US-7,922,818 Method and system for binding halide-based contaminants
A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized...
US-7,922,562 Systems and methods for reducing electrostatic charge of semiconductor wafers
A chemical-mechanical polishing machine and associated methods are disclosed. One embodiment of the machine includes a polishing pad, a wafer carrier...
US-7,920,431 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-7,920,428 Methods and apparatuses relating to automatic cell threshold voltage measurement
Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current...
US-7,920,427 Dynamic soft program trims
Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming...
US-7,920,185 Shielding black reference pixels in image sensors
An image sensor having an array of pixel cells, each including a photo-conversion device. The array has first, second, and third groups of pixel cells. The...
US-7,919,999 Band-gap reference voltage detection circuit
Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage...
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