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Epitaxial silicon growth
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon...
Memory array with a pair of memory-cell strings to a single conductive
Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second...
Methods for forming small-scale capacitor structures
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a...
Label peeling method for label paper sheet and label printer
A label peeling method for label sheet includes: conveying a label sheet including a base sheet and a label affixed to the base sheet along a conveying path that...
Powder processing apparatus
In order to manufacture the compound powder or the porous granulated substance in an efficient manner, a powder processing apparatus has an accumulating face on...
Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
Memory array segmentation and methods
An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on...
Increased NAND flash memory read throughput
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and...
Sensing for memory read and program verify operations in a non-volatile
Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple...
Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be...
Compensation capacitor network for divided diffused resistors for a
A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is...
Phase mixer with adjustable load-to-drive ratio
Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals...
Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
Interposer configured to reduce the profiles of semiconductor device
assemblies, packages including the same,...
An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may...
Microfeature workpieces having interconnects and conductive backplanes,
and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
Two-sided surround access transistor for a 4.5F2 DRAM cell
An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide...
Tantalum lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of...
Assemblies comprising magnetic elements and magnetic barrier or shielding
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
Dielectric layers and memory cells including metal-doped alumina
A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate...
Silicon dioxide deposition methods using at least ozone and TEOS as
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In...
Methods of etching polysilicon and methods of forming pluralities of
A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal...
Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region....
Methods of fabricating dual fin structures
Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source...
Methods of forming field effect transistors, methods of forming field
effect transistor gates, methods of...
The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry...
Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
Memory system and method using ECC with flag bit to identify modified data
A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also...
Enabling test modes of individual integrated circuit devices out of a
plurality of integrated circuit devices
Methods and apparatus are provided. A common test-mode enable signal is received at two or more integrated circuit devices of an electronic system. A test mode...
Matrix modeling of parallel data structures to facilitate data encoding
and/or jittery signal generation
A computer-implementable method comprises a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors...
Method for controlling clock cycle time for reduced power consumption in a
semiconductor memory device
Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the...
Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
Analog sensing of memory cells in a solid state memory device
A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected...
Method, apparatus, and system for improved read operation in memory
Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold...
Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
Use of emerging non-volatile memory elements with flash memory
Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic...
Memory structure having volatile and non-volatile memory portions
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates...
Memory cell heights
Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number...
Memory cells, electronic systems, methods of forming memory cells, and
methods of programming memory cells
Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may...
Dual conversion gain gate and capacitor and HDR combination
A pixel circuit having a shared control line for providing two control signals to the pixel array. One control line is used to provide a control signal to both a...
An amplifier circuit with favorable linearity is provided.An amplifier of the present invention is provided with an amplifier MOS transistor, a diode-connected...
High slew rate amplifier, analog-to-digital converter using same, CMOS
imager using the analog-to-digital...
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one...
Apparatus and method for trimming static delay of a synchronizing circuit
A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals...
At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives...
Method and apparatus for high resolution ZQ calibration
A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is...
Methods for forming through wafer interconnects and structures resulting
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
Scalable multi-functional and multi-level nano-crystal non-volatile memory
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two...
Semiconductor constructions having multiple patterned masking layers over
NAND gate stacks
Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string...
Floating-gate memory cell and memory device and electronic system
A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the...
Transparent conductor based pinned photodiode
A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region...
Multi-level programmable PCRAM memory
A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to...