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Patent # Description
US-7,907,468 Memory device having data paths permitting array/port consolidation and swapping
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads...
US-7,907,444 Memory device reference cell programming method and apparatus
Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example,...
US-7,906,853 Package structure for multiple die stack
A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first...
US-7,906,830 Epitaxial silicon growth
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon...
US-7,906,818 Memory array with a pair of memory-cell strings to a single conductive pillar
Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second...
US-7,906,393 Methods for forming small-scale capacitor structures
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a...
US-7,905,976 Label peeling method for label paper sheet and label printer
A label peeling method for label sheet includes: conveying a label sheet including a base sheet and a label affixed to the base sheet along a conveying path that...
US-7,905,434 Powder processing apparatus
In order to manufacture the compound powder or the porous granulated substance in an efficient manner, a powder processing apparatus has an accumulating face on...
US-7,903,488 Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
US-7,903,464 Memory array segmentation and methods
An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on...
US-7,903,463 Increased NAND flash memory read throughput
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and...
US-7,903,461 Sensing for memory read and program verify operations in a non-volatile memory device
Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple...
US-7,903,379 Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be...
US-7,902,907 Compensation capacitor network for divided diffused resistors for a voltage divider
A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is...
US-7,902,896 Phase mixer with adjustable load-to-drive ratio
Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals...
US-7,902,875 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,902,648 Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same,...
An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may...
US-7,902,643 Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a...
US-7,902,598 Two-sided surround access transistor for a 4.5F2 DRAM cell
An isolation transistor having a grounded gate is formed between a first access transistor construction and a second access transistor construction to provide...
US-7,902,582 Tantalum lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of...
US-7,902,580 Assemblies comprising magnetic elements and magnetic barrier or shielding
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
US-7,902,099 Dielectric layers and memory cells including metal-doped alumina
A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,902,084 Silicon dioxide deposition methods using at least ozone and TEOS as deposition precursors
Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In...
US-7,902,081 Methods of etching polysilicon and methods of forming pluralities of capacitors
A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal...
US-7,902,074 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region....
US-7,902,057 Methods of fabricating dual fin structures
Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source...
US-7,902,028 Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of...
The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry...
US-7,900,162 Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
US-7,900,120 Memory system and method using ECC with flag bit to identify modified data
A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also...
US-7,900,099 Enabling test modes of individual integrated circuit devices out of a plurality of integrated circuit devices
Methods and apparatus are provided. A common test-mode enable signal is received at two or more integrated circuit devices of an electronic system. A test mode...
US-7,899,653 Matrix modeling of parallel data structures to facilitate data encoding and/or jittery signal generation
A computer-implementable method comprises a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors...
US-7,898,901 Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device
Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the...
US-7,898,892 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,898,885 Analog sensing of memory cells in a solid state memory device
A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected...
US-7,898,863 Method, apparatus, and system for improved read operation in memory
Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold...
US-7,898,861 Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
US-7,898,859 Use of emerging non-volatile memory elements with flash memory
Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic...
US-7,898,857 Memory structure having volatile and non-volatile memory portions
A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates...
US-7,898,856 Memory cell heights
Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number...
US-7,898,850 Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells
Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may...
US-7,898,588 Dual conversion gain gate and capacitor and HDR combination
A pixel circuit having a shared control line for providing two control signals to the pixel array. One control line is used to provide a control signal to both a...
US-7,898,339 Amplifier circuit
An amplifier circuit with favorable linearity is provided.An amplifier of the present invention is provided with an amplifier MOS transistor, a diode-connected...
US-7,898,337 High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital...
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one...
US-7,898,308 Apparatus and method for trimming static delay of a synchronizing circuit
A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals...
US-7,898,294 Pre-driver logic
At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives...
US-7,898,290 Method and apparatus for high resolution ZQ calibration
A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is...
US-7,898,064 Methods for forming through wafer interconnects and structures resulting therefrom
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
US-7,898,062 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,898,022 Scalable multi-functional and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two...
US-7,898,019 Semiconductor constructions having multiple patterned masking layers over NAND gate stacks
Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string...
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