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Patent # Description
US-7,915,718 Apparatus for flip-chip packaging providing testing capability
A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating...
US-7,915,711 Semiconductor assemblies and methods of manufacturing such assemblies including trenches in a molding material...
Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of...
US-7,915,692 Semiconductor structure including gateline surrounding source and drain pillars
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,915,673 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-7,915,669 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,915,659 Devices with cavity-defined gates and methods of making the same
A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a...
US-7,915,174 Dielectric stack containing lanthanum and hafnium
Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in...
US-7,915,168 Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
US-7,915,126 Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
US-7,915,116 Relaxed-pitch method of aligning active area to digit line
According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at...
US-7,915,077 Methods of making metal core foldover package structures
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked ...
US-7,913,062 Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
US-7,913,035 Method and apparatus for address FIFO for high bandwidth command/address busses in digital storage system
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a...
US-7,913,033 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The...
US-7,912,671 Method for measuring the position of a mark in a deflector system
The present invention relates to a method for determining the coordinates of an arbitrarily shaped pattern in a deflector system. The method basically comprises...
US-7,911,872 Column/row redundancy architecture using latches programmed from a look up table
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
US-7,911,865 Temperature compensation of memory signals using digital signals
A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates...
US-7,911,837 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,911,819 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of...
US-7,911,245 Multi-phase signal generator and method
A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals...
US-7,910,972 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
US-7,910,971 Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the...
US-7,910,905 Self-aligned, planar phase change memory elements and devices
Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second...
US-7,910,660 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
US-7,910,487 Reverse masking profile improvements in high aspect ratio etch
A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of...
US-7,910,483 Trim process for critical dimension control for integrated circuits
Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of...
US-7,910,426 Pixel and imager device having high-k dielectrics in isolation structures
An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention...
US-7,910,397 Small electrode for resistance variable devices
A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a...
US-7,910,385 Method of fabricating microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a...
US-7,910,288 Mask material conversion
The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form...
US-7,910,270 Reticle constructions
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-7,908,451 Memory command delay balancing in a daisy-chained memory topology
A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the...
US-7,907,928 High speed, wide frequency-range, digital phase mixer and methods of operation
The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output...
US-7,907,468 Memory device having data paths permitting array/port consolidation and swapping
Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads...
US-7,907,444 Memory device reference cell programming method and apparatus
Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example,...
US-7,906,853 Package structure for multiple die stack
A die module and method for assembling such a die module is provided. For example, present embodiments include providing a substrate and coupling a first...
US-7,906,830 Epitaxial silicon growth
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon...
US-7,906,818 Memory array with a pair of memory-cell strings to a single conductive pillar
Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second...
US-7,906,393 Methods for forming small-scale capacitor structures
The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a...
US-7,905,976 Label peeling method for label paper sheet and label printer
A label peeling method for label sheet includes: conveying a label sheet including a base sheet and a label affixed to the base sheet along a conveying path that...
US-7,905,434 Powder processing apparatus
In order to manufacture the compound powder or the porous granulated substance in an efficient manner, a powder processing apparatus has an accumulating face on...
US-7,903,488 Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
US-7,903,464 Memory array segmentation and methods
An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on...
US-7,903,463 Increased NAND flash memory read throughput
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and...
US-7,903,461 Sensing for memory read and program verify operations in a non-volatile memory device
Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple...
US-7,903,379 Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be...
US-7,902,907 Compensation capacitor network for divided diffused resistors for a voltage divider
A voltage divider of a voltage regulator system is disclosed utilizing divided diffused resistors. In one embodiment, a feed-forward capacitor network is...
US-7,902,896 Phase mixer with adjustable load-to-drive ratio
Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals...
US-7,902,875 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,902,648 Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same,...
An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may...
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