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Patent # Description
US-7,882,306 Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring...
US-7,881,149 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,881,134 Replacing defective columns of memory cells in response to external addresses
Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a...
US-7,881,113 Relaxed metal pitch memory architectures
A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to...
US-7,881,100 State machine sensing of memory cells
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating...
US-7,881,051 Memory module and cover therefor
A storage device has a memory module enclosed within a housing and a removable cover. In a first configuration of the storage device, while leaving a portion of...
US-7,880,531 System, apparatus, and method for selectable voltage regulation
Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current...
US-7,880,307 Semiconductor device including through-wafer interconnect structure
Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may...
US-7,880,267 Buried decoupling capacitors, devices and systems including same, and methods of fabrication
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a...
US-7,880,255 Pixel cell having a grated interface
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with...
US-7,880,232 Processes and apparatus having a semiconductor fin
A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch...
US-7,879,674 Germanium-silicon-carbide floating gates in memories
The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in...
US-7,879,659 Methods of fabricating semiconductor devices including dual fin structures
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-7,879,649 Programmable capacitor associated with an input/output pad
The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus...
US-7,879,646 Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming...
The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at...
US-7,877,669 Non-volatile memory with error detection
Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated...
US-7,877,612 System and method for controlling user access to an electronic device
A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and...
US-7,877,530 Bus width negotiation
There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad...
US-7,876,640 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit...
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock ...
US-7,876,639 Memory devices having redundant arrays for repair
Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes...
US-7,876,638 Storing operational information in an array of memory cells
The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment...
US-7,876,623 Program method with optimized voltage level for flash memory
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the...
US-7,876,622 Read method for MLC
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-7,876,603 Spin current generator for STT-MRAM or other spintronics applications
Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current...
US-7,876,597 NAND-structured series variable-resistance material memories, processes of forming same, and methods of using same
A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory...
US-7,875,912 Zr.sub.x Hf.sub.y Sn.sub.1-x-y O.sub.2 films as high k gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) and tin oxide (SnO.sub.2)...
US-7,875,821 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,875,529 Semiconductor devices
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for...
US-7,875,110 Electroless plating bath composition and method of use
An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An...
US-7,873,882 Circuits and methods for repairing defects in memory devices
Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The...
US-7,872,926 Input buffer and method with AC positive feedback, and a memory device and computer system using same
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative...
US-7,872,924 Multi-phase duty-cycle corrected clock signal generator and memory having same
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such...
US-7,872,923 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may...
US-7,872,920 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based...
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line...
US-7,872,912 M+N bit programming and M+L bit read for M bit memory cells
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage...
US-7,872,911 Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of...
US-7,872,682 Eclipse elimination by monitoring the pixel signal level
An anti-eclipse circuit for an imaging sensor monitors the photo signal level output by a pixel to determine whether the photo signal corresponds to the pixel...
US-7,872,676 Methods, systems, and devices for offset compensation in CMOC imagers
Methods, devices, and systems for offset compensation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of...
US-7,872,507 Delay lines, methods for delaying a signal, and delay lock loops
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of...
US-7,872,332 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and...
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system...
US-7,872,284 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,871,911 Methods for fabricating semiconductor device structures
Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may...
US-7,870,351 System, apparatus, and method for modifying the order of memory accesses
Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices....
US-7,870,330 Controller for refreshing memories
A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device...
US-7,870,329 System and method for optimizing interconnections of components in a multichip memory module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have...
US-7,869,494 Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI)...
US-7,869,457 High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
US-7,869,285 Low voltage operation bias current generation circuit
Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a...
US-7,869,249 Complementary bit PCRAM sense amplifier and method of operation
A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM...
US-7,869,242 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
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