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Patent # Description
US-7,955,836 Microfluidic mixing and analytical apparatus
Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles...
US-7,955,764 Methods to make sidewall light shields for color filter array
Methods of forming color filters having a light blocking material therebetween. A color filter is formed such that a trench is defined between a color filter...
US-7,954,029 System, apparatus, and method for memory built-in self testing using microcode sequencers
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions...
US-7,954,004 Systems and methods for retrieving data
Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques...
US-7,953,954 Flash storage partial page caching
Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device...
US-7,953,579 Jittery signal generation with discrete-time filtering
The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the...
US-7,952,952 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,952,936 Program-verify method
Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory...
US-7,952,927 Adjusting program and erase voltages in a memory device
A method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. A method...
US-7,952,924 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
US-7,952,922 Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect
A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data....
US-7,952,919 Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
US-7,952,913 Back gated SRAM cell
One method for operating an SRAM cell includes applying a potential to a back gate of a pair of cross coupled p-type pull up transistors in the SRAM during a...
US-7,952,631 CMOS imager with integrated circuitry
A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS...
US-7,952,184 Distributed semiconductor device methods, apparatus, and systems
Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be...
US-7,952,174 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles
A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is...
US-7,952,171 Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a...
US-7,952,170 System including semiconductor components having through interconnects and back side redistribution conductors
A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a...
US-7,952,169 Isolation circuit
An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the...
US-7,952,158 Elevated pocket pixels, imaging devices and systems including the same and method of forming the same
An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,...
US-7,952,155 Reduced edge effect from recesses in imagers
Methods for making a recessed color filter array for a semiconductor imager employing a sidewall spacer for reducing an edge effect from the array are...
US-7,951,709 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
US-7,951,702 Methods for fabricating semiconductor components with conductive interconnects having planar surfaces
A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a...
US-7,951,619 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over...
US-7,951,414 Methods of forming electrically conductive structures
Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect...
US-7,949,844 Pipelined burst memory access
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to...
US-7,949,822 Storage capacity status
In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated...
US-7,949,821 Method of storing data on a flash memory device
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block...
US-7,949,803 System and method for transmitting data packets in a computer system having a memory hub architecture
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled...
US-7,948,821 Reduced signal interface memory device, system, and method
A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad....
US-7,948,802 Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
US-7,948,793 Temperature compensation in memory devices and systems
Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A...
US-7,948,786 Rank select using a global select pin
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system,...
US-7,948,279 Clock divider
There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six....
US-7,948,030 Semiconductor constructions of memory devices with different sizes of GateLine trenches
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.3. The recessed...
US-7,948,008 Floating body field-effect transistors, and methods of forming floating body field-effect transistors
In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween....
US-7,947,601 Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device
Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for...
US-7,947,597 Methods of titanium deposition
Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to...
US-7,947,543 Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This...
US-7,947,529 Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages,...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of...
US-7,947,412 Reduced lens heating methods, apparatus, and systems
In one embodiment, a system is disclosed that includes an illuminator having a source that produces light waves having a first wavelength, and a mask. The mask...
US-7,946,855 Contact and electrical connecting apparatus
A contact type electrical connector includes a first plunger in contact with one member; a second plunger in contact with another member and electrically...
US-7,945,840 Memory array error correction apparatus, systems, and methods
Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being...
US-7,944,773 Synchronous command-based write recovery time auto-precharge control
Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous...
US-7,944,768 Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
US-7,944,764 Writing to non-volatile memory during a volatile memory refresh cycle
Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write...
US-7,944,762 Non-volatile memory control
Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a...
US-7,944,761 Memory device having strobe terminals with multiple functions
A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device...
US-7,944,757 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method...
US-7,944,755 Erase verify in memory devices
In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a...
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