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Patent # Description
US-9,543,166 External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be...
US-9,543,003 Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
US-9,543,000 Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of...
US-9,542,985 Channel skewing
The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data...
US-9,542,242 Efficient operations of components in a wireless communications device
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the...
US-9,542,121 Memory device using extended interface commands
A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes...
US-9,542,102 Stacked memory devices, systems, and methods
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-9,538,724 Ear tag for recognizing livestock individual
An ear tag for recognizing livestock individual is provided. The ear tag for recognizing livestock individual according to the present invention includes a...
US-9,537,091 Structures for resistance random access memory and methods of forming the same
Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor...
US-9,537,088 Magnetic tunnel junctions
Some embodiments include a magnetic tunnel junction comprising magnetic reference material having an iridium-containing region between a multi-layer stack and a...
US-9,536,971 Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls
A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention...
US-9,536,940 Interfacial materials for use in semiconductor structures and related methods
A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the...
US-9,536,823 Conductive structures, systems and devices including conductive structures and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
US-9,536,817 Electronic devices and methods of manufacturing electronic devices
Disclosed are a foldable and spreadable electronic device and a method of manufacturing the electronic device. The electronic device may include a flexible...
US-9,536,618 Apparatuses and methods to control body potential in memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
US-9,536,603 Methods and apparatuses for determining threshold voltage shift
Apparatuses and methods for determining threshold voltage shift are described. A number of methods for determining threshold voltage shift in memory cells...
US-9,536,591 Staggered DLL clocking on N-Detect QED to minimize clock command and delay path
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus...
US-9,536,582 Enable/disable of memory chunks during memory access
Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed...
US-9,535,876 Conditional operation in an internal processor of a memory device
An internal processor of a memory device configured to selectively execute instructions in parallel. One such internal processor includes a plurality of...
US-9,535,861 Methods and systems for routing in a state machine
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
US-9,535,108 Inspection apparatus and inspection method
An inspection apparatus for inspecting an inspection object. The inspection object includes a base body and wiring passing through the base body. The inspection...
US-9,535,090 Electric connecting apparatus
An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe...
US-9,531,364 Two-stage phase mixer circuit
Apparatuses and methods are directed to preventing duty cycle distortion in an electronic apparatus. The apparatus generally includes a first phase mixer stage...
US-9,531,363 Methods and apparatuses including command latency control circuit
Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal,...
US-9,530,959 Magnetic tunnel junctions
A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic MgO-comprising material over conductive material of the...
US-9,530,927 Light emitting devices with built-in chromaticity conversion and methods of manufacturing
Various embodiments of light emitting devices with built-in chromaticity conversion and associated methods of manufacturing are described herein. In one...
US-9,530,842 Semiconductor devices
Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region...
US-9,530,837 Integrated circuitry and methods of forming transistors
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second...
US-9,530,794 Apparatuses having a ferroelectric field-effect transistor memory array and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates...
US-9,530,748 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-9,530,683 Forming source/drain zones with a dielectric plug over an isolation region between active regions
An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second...
US-9,530,497 Systems, methods and devices for programming a multilevel resistive memory cell
Embodiments disclosed herein may relate to programming a multi-level memory cell with programming pulse sequences that comprise forward-biased and...
US-9,530,477 Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT...
US-9,530,475 Independently addressable memory array address spaces
Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address...
US-9,530,473 Apparatuses and methods for timing provision of a command to input circuitry
An apparatus or method may include provision of a command to a data block. An example apparatus includes a command circuit configured to provide a command...
US-9,530,470 Method and apparatus for pre-charging data lines in a memory cell array
Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the...
US-9,530,459 Semiconductor memory device including a repeater circuit on main data lines
A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from...
US-9,530,327 System and method for managing continued attention to distance-learning content
Management of a user's continued attention to distance learning content using a general purpose computer having a central processing unit, an operating system...
US-9,529,736 Apparatus, electronic devices and methods associated with an operative transition from a first interface to a...
Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in...
US-9,529,734 Smart storage device
A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the...
US-9,529,713 Line termination methods and apparatus
Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance...
US-9,529,379 Timing synchronization circuit with loop counter
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter....
US-9,525,341 Ladder-based high speed switch regulator
Some embodiments include apparatuses having a switch regulator that includes a first circuit with a first comparator to compare an output of the switch...
US-9,525,131 Memory devices having electrodes comprising nanowires
Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to...
US-9,525,007 Phase change memory device with voltage control elements
A phase change memory device with reduced programming disturbance and its operation are described. The phase change memory includes an array with word lines and...
US-9,524,875 Methods of etching trenches into silicon of a semiconductor substrate
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-9,524,759 Apparatuses and methods for capturing data using a divided clock
Apparatuses and methods for capturing data using a divided clock are described. An example apparatus includes a clock divider configured to receive a DQS...
US-9,524,756 Apparatuses and methods for coupling semiconductor devices of a memory module in a memory system
A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error....
US-9,524,254 Multi-serial interface stacked-die memory architecture
Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding...
US-9,524,250 Block or page lock features in serial interface memory
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a...
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