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Patent # Description
US-1,002,6680 Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
US-1,002,6643 Methods of forming nanofluidic channels
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,002,6480 Memory device including multiple select gates and different bias conditions
Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string...
US-1,002,6462 Apparatuses and methods for providing constant DQS-DQ delay in a memory device
Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line...
US-1,002,6459 Data gathering in memory
Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of...
US-1,002,6458 Memories and methods for performing vector atomic memory operations with mask control and variable data length...
Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder....
US-1,002,6457 Device having multiple channels with calibration circuit shared by multiple channels
An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second...
US-1,002,6026 Printer, printing system and print control method
The present invention enables successful printing whether printing data contains a character code of either code page or Unicode without an addition of an...
US-1,002,5593 Generating and executing a control flow
The present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device...
US-1,002,4908 Probe and contact inspection device
A probe comprises a first end that contacts and separates from a test object and a second end that contacts a circuit board to perform inspection of the test...
US-1,002,0446 Methods of forming magnetic memory cells and semiconductor devices
A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be...
US-1,002,0432 Etched trenches in bond materials for die singulation, and associated systems and methods
Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation...
US-1,002,0360 Integrated memory
Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the...
US-1,002,0310 Memory device and fabricating method thereof
A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a...
US-1,002,0289 Layout of transmission vias for memory device
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory...
US-1,002,0287 Pass-through interconnect structure for microelectronic dies and associated systems and methods
Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die...
US-1,002,0252 Wiring with external terminal
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality...
US-1,002,0228 Integrated circuitry and methods of forming transistors
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second...
US-1,002,0058 Memory as a programmable logic device
Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of...
US-1,002,0056 Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
US-1,002,0046 Stack refresh control for memory device
Apparatuses and methods for self-refreshing a plurality of dies are described. An example apparatus includes a first die including a first bank and a second...
US-1,002,0045 Partial access mode for dynamic random access memory
Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to...
US-1,002,0038 Apparatuses and methods for controlling wordlines and sense amplifiers
Apparatuses for controlling defective bit lines in a semiconductor device are described. An example apparatus includes: a first region including a plurality of...
US-1,002,0033 Indirect register access method and system
Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The...
US-1,001,9369 Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested...
US-1,001,9311 Validation of a symbol response memory
Configuration content of electronic devices used for data analysis may be altered due to bit failure or corruption, for example. Accordingly, in one embodiment,...
US-1,001,9310 Error correction in multiple semiconductor memory units
Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second...
US-1,001,9170 Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed...
In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock...
US-1,001,8669 Electrical contactor and electrical connecting apparatus
An electrical contactor of this invention includes: a first plunger to contact one member, the first plunger including a tip portion formed into a plurality of...
US-1,001,5027 Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures
Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include...
US-1,001,4861 Level shifters, memory systems, and level shifting methods
Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive...
US-1,001,4466 Semiconductor devices with magnetic and attracter materials and methods of fabrication
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
US-1,001,4347 Arrays of memory cells and methods of forming an array of memory cells
An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced...
US-1,001,4345 Magnetic memory device with grid-shaped common source plate, system, and method of fabrication
Magnetic memory devices include an array of magnetic memory cells including magnetic tunnel junction regions. The array of magnetic memory cells includes access...
US-1,001,4319 Conductive components and memory assemblies
Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is...
US-1,001,4311 Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon,...
A method of forming poly silicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material...
US-1,001,4309 Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge...
An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a...
US-1,001,4305 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in...
US-1,001,4302 Methods of forming memory arrays
Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material....
US-1,001,4301 Semiconductor constructions
Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces....
US-1,001,4281 Methods of manufacturing a semiconductor device package including a controller element
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
US-1,001,4211 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,001,4115 Apparatuses, multi-chip modules and capacitive chips
Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and...
US-1,001,4070 Data path integrity verification in memory devices
Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device...
US-1,001,4062 Apparatus and methods for determining a pass/fail condition of a memory device
Memory devices including an array of memory cells, a first buffer selectively connected to the array of memory cells and corresponding to a particular bit rank...
US-1,001,4061 Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in...
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory...
US-1,001,4057 Devices including memory arrays, row decoder circuitries and column decoder circuitries
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data...
US-1,001,4053 Methods for backup sequence using three transistor memory cell devices
Methods for a backup sequence includes reading first data from a first data memory to a page buffer, copying the first data from the page buffer to a backup...
US-1,001,4051 Data storage with data randomizer in multiple operating modes
Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and...
US-1,001,4038 Apparatuses and methods for chip identification in a memory package
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer...
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