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Patent # Description
US-7,864,585 Multi level inhibit scheme
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions...
US-7,864,584 Expanded programming window for non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel...
US-7,864,577 Sharing physical memory locations in memory devices
A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of...
US-7,864,575 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,864,457 Achromatic lens structure, method of fabrication, and imaging devices and systems using the same
Lens structures, imaging devices, and methods of making the same that include a lens and a transparent material having different dispersions and used to correct...
US-7,864,294 Focus sensitive lithographic apparatus, systems, and methods
A system includes an illuminator, a mask, and a measurement device. The illuminator includes a light source. The mask includes at least one focus determination...
US-7,863,924 Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using...
Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment...
US-7,863,727 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a...
US-7,863,722 Stackable semiconductor assemblies and methods of manufacturing such assemblies
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor...
US-7,863,667 Zirconium titanium oxide films
Dielectric layers having an atomic layer deposited oxide containing titanium and zirconium and a method of fabricating such a dielectric layer produce a reliable...
US-7,863,663 Hybrid electrical contact
Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A...
US-7,863,597 Resistance variable memory devices with passivating material
A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide...
US-7,863,595 Reproducible resistance variable insulating memory devices having a shaped bottom electrode
The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the...
US-7,863,199 Methods of forming particle-containing materials
The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials....
US-7,863,198 Method and device to vary growth rate of thin films over semiconductor structures
Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use...
US-7,863,187 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature...
US-7,863,176 Low-resistance interconnects and methods of making same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
US-7,863,133 Oxide epitaxial isolation
Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming...
US-7,862,964 Methods for photo-processing photo-imageable material
The invention includes methods for photo-processing photo-imageable material. Locations of the photo-imageable material where flare hot spots are expected to...
US-7,862,733 Method for manufacturing a probe
The present invention provides a probe manufacturing method in which, after a metal material for a probe is deposited on a base table, the probe can be detached...
US-7,862,316 Foamed mechanical planarization pads made with supercritical fluid
Foamed thermoplastic polymeric mechanical planarization polishing pads ("MP pads") made with supercritical fluids are presented. A supercritical fluid foaming...
US-7,862,232 Temperature sensor, device and system including same, and method of operation
A temperature sensor and device and system including same, comprise a switched capacitor circuit configured to generate a noise voltage in response to switching...
US-7,861,139 Programming management data for NAND memories
Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a...
US-7,860,294 Magnetic ink character reading apparatus and method of controlling the same
A magnetic ink character reading apparatus includes a similarity acquisition unit, a character recognition unit and a character recognition limiting unit. The...
US-7,859,922 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,859,916 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a...
US-7,859,893 Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
US-7,859,888 Resistive memory device
A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage...
US-7,859,295 Transmitter apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost...
US-7,859,282 Electrical connecting apparatus
An electrical connecting apparatus for use in electrical measurement of a device under test comprises a supporting member and a flat plate-like probe base plate....
US-7,859,112 Additional metal routing in semiconductor devices
Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate...
US-7,859,050 Memory having a vertical access device
Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a...
US-7,859,046 Ballistic direct injection NROM cell on strained silicon structures
A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the...
US-7,859,036 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form...
US-7,858,815 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds
A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,858,535 Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes and...
Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished...
US-7,858,523 Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In some...
US-7,858,518 Method for forming a selective contact and local interconnect in situ
A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of...
US-7,858,506 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-7,858,486 Methods of forming a plurality of capacitors
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,858,471 Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery...
Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having...
US-7,858,468 Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant...
US-7,858,458 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-7,858,420 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,857,982 Methods of etching features into substrates
The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A...
US-7,857,646 Electrical testing apparatus having masked sockets and associated systems and methods
An apparatus for forming a temporary electrical connection with a microelectronic component and associated systems and methods are disclosed herein. Embodiments...
US-7,856,888 Fiber optic strain gage and carrier
The current invention relates to optical gages designed to measure strain on the surface of a test specimen. The gages of this invention is designed to be...
US-7,855,931 Memory system and method using stacked memory device dice, and system using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is...
US-7,855,928 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,855,927 NAND system with a data write frequency greater than a command-and-address-load frequency
The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second...
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