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Patent # Description
US-7,892,978 Electron induced chemical etching for device level diagnosis
A method of imaging and identifying materials, contamination, fabrication errors, and defects on and below the surface of an integrated circuit (IC) is...
US-7,892,972 Methods for fabricating and filling conductive vias and conductive vias so formed
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers,...
US-7,892,964 Vapor deposition methods for forming a metal-containing layer on a substrate
Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as...
US-7,892,943 Isolation trenches for memory devices
A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug...
US-7,892,942 Methods of forming semiconductor constructions, and methods of forming isolation regions
Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing...
US-7,892,941 Technique for forming shallow trench isolation structure without corner exposure
A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a...
US-7,892,937 Methods of forming capacitors
Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of...
US-7,892,921 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate...
US-7,890,819 Method and apparatus for storing failing part locations in a module
A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module,...
US-7,889,562 Adjusting programming or erase voltage pulses in response to a rate of programming or erasing
Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to...
US-7,889,561 Read operation for NAND memory
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively...
US-7,888,991 Clock distribution network
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide...
US-7,888,958 Current test probe having a solder guide portion, and related probe assembly and production method
A probe for current test is provided. The probe includes a probe body having a plate-like connection portion whose end face becomes a connection face to a probe...
US-7,888,774 Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and...
US-7,888,744 Strained semiconductor, devices and systems and methods of formation
In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The...
US-7,888,721 Surround gate access transistors with grown ultra-thin bodies
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid...
US-7,888,255 Method of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry
A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through...
US-7,888,188 Method of fabicating a microelectronic die having a curved surface
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a...
US-7,888,185 Semiconductor device assemblies and systems including at least one conductive pathway extending around a side...
Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over...
US-7,888,165 Methods of forming a phase change material
Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias...
US-7,885,782 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed...
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is...
US-7,885,128 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-7,884,630 IC carrie, IC socket and method for testing IC device
An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a...
US-7,884,629 Probe card layout
Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater efficiency during testing of a substrate having a plurality of die...
US-7,884,405 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,884,311 Imaging devices having a layer of pixel component material with discrete constructs for operating electrical...
Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer...
US-7,884,015 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
US-7,884,007 Super high density module with integrated wafer level packages
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of...
US-7,883,986 Methods of forming trench isolation and methods of forming arrays of FLASH memory cells
This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is...
US-7,883,962 Trench DRAM cell with vertical device and buried word lines
A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for...
US-7,883,959 Semiconductor processing methods
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a...
US-7,883,931 Methods of forming memory cells, and methods of forming programmed memory cells
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region;...
US-7,883,927 Method and apparatus to sort nanotubes
Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube...
US-7,883,908 Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)
A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first...
US-7,883,907 Parameter measurement using multi-layer structures
Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay...
US-7,883,745 Chemical vaporizer for material deposition systems and associated methods
System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a...
US-7,882,306 Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring...
US-7,881,149 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,881,134 Replacing defective columns of memory cells in response to external addresses
Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a...
US-7,881,113 Relaxed metal pitch memory architectures
A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to...
US-7,881,100 State machine sensing of memory cells
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating...
US-7,881,051 Memory module and cover therefor
A storage device has a memory module enclosed within a housing and a removable cover. In a first configuration of the storage device, while leaving a portion of...
US-7,880,531 System, apparatus, and method for selectable voltage regulation
Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current...
US-7,880,307 Semiconductor device including through-wafer interconnect structure
Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may...
US-7,880,267 Buried decoupling capacitors, devices and systems including same, and methods of fabrication
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a...
US-7,880,255 Pixel cell having a grated interface
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with...
US-7,880,232 Processes and apparatus having a semiconductor fin
A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch...
US-7,879,674 Germanium-silicon-carbide floating gates in memories
The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in...
US-7,879,659 Methods of fabricating semiconductor devices including dual fin structures
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-7,879,649 Programmable capacitor associated with an input/output pad
The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus...
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