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Patent # Description
US-7,944,748 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,944,743 Methods of making a semiconductor memory device
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base...
US-7,944,738 Spin torque transfer cell structure utilizing field-induced antiferromagnetic or ferromagnetic coupling
A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a...
US-7,944,485 Method, apparatus and system for dynamic range estimation of imaged scenes
A method, apparatus, and system for dynamic range estimation of imaged scenes for automatic exposure control. For a given exposure time setting, certain areas...
US-7,944,300 Bias circuit and amplifier providing constant output current for a range of common mode inputs
Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a...
US-7,944,234 Programmable on-chip logic analyzer apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to...
US-7,944,025 Semiconductor constructions
The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a...
US-7,944,019 Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
US-7,943,921 Phase change current density control structure
A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is...
US-7,943,505 Advanced VLSI metallization
A four layer interconnect structure is disclosed which includes a bottom conductive reactive layer such as titanium, a conductive barrier layer, such as...
US-7,943,503 Trench interconnect structure and formation method
Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in...
US-7,943,501 Systems and methods of forming tantalum silicide layers
A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion...
US-7,943,463 Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon
A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular...
US-7,943,422 Wafer level pre-packaged flip chip
Methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer are provided. An embodiment of the method includes applying...
US-7,941,712 Method for error test, recordation and repair
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test....
US-7,941,056 Optical interconnect in high-speed memory systems
A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of...
US-7,940,569 Power off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
US-7,940,568 Dynamic polarization for reducing stress induced leakage current
Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current.
US-7,940,559 Memory array having a programmable word length, and method of operating same
A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or...
US-7,940,556 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,940,103 Duty cycle correction systems and methods
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a...
US-7,940,078 Method and apparatus for output driver calibration, and memory devices and system embodying same
A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration...
US-7,939,949 Semiconductor device with copper wirebond sites and methods of making same
Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a...
US-7,939,948 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,...
US-7,939,877 DRAM unit cells, capacitors, methods of forming DRAM unit cells, and methods of forming capacitors
Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A...
US-7,939,449 Methods of forming hybrid conductive vias including small dimension active surface ends and larger dimension...
A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a...
US-7,939,442 Strontium ruthenium oxide interface
Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium...
US-7,939,409 Peripheral gate stacks and recessed array gates
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic...
US-7,939,403 Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry...
A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a...
US-7,939,394 Multiple-depth STI trenches in integrated circuit fabrication
Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths....
US-7,937,576 Configuration of a multi-level flash memory device
A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the...
US-7,936,955 Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
US-7,936,812 Fractional-rate decision feedback equalization useful in a data transmission system
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a...
US-7,936,639 System and method for processing signals in high speed DRAM
A method is disclosed for operating a memory device, including providing a timing signal comprising a plurality of clock cycles, providing an activate signal,...
US-7,936,637 System and method for synchronizing asynchronous signals without external clock
One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an...
US-7,936,610 Selective refresh of single bit memory cells
Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans...
US-7,936,608 Memory device operation
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines...
US-7,936,606 Compensation of back pattern effect in a memory device
In one or more of provided embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases...
US-7,936,599 Coarse and fine programming in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,936,203 Temperature compensation via power supply modification to produce a temperature-independent delay in an...
A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated...
US-7,936,199 Apparatus and method for external to internal clock generation
A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first...
US-7,936,058 Stacked package and method for forming stacked package
The present invention provides an inexpensive semiconductor chip module enabling sufficient heat dissipation without complicating the manufacture process. A...
US-7,936,000 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,935,999 Memory device
A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are...
US-7,935,997 Low resistance peripheral contacts while maintaining DRAM array integrity
An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM...
US-7,935,991 Semiconductor components with conductive interconnects
A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a...
US-7,935,639 Process for increasing feature density during the manufacture of a semiconductor device
Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each...
US-7,935,633 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,935,618 Sputtering-less ultra-low energy ion implantation
Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering...
US-7,935,610 Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a...
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