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Patent # Description
US-7,876,640 Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit...
Memories, clock synchronization circuits, clock synchronization controller circuits, and methods for setting a voltage controlled delay of a clock ...
US-7,876,639 Memory devices having redundant arrays for repair
Apparatus and methods are disclosed, such as those involving a memory device. One such memory device includes a memory array including a sub-array that includes...
US-7,876,638 Storing operational information in an array of memory cells
The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment...
US-7,876,623 Program method with optimized voltage level for flash memory
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the...
US-7,876,622 Read method for MLC
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-7,876,603 Spin current generator for STT-MRAM or other spintronics applications
Spin current generators and systems and methods for employing spin current generators. A spin current generator may be configured to generate a spin current...
US-7,876,597 NAND-structured series variable-resistance material memories, processes of forming same, and methods of using same
A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory...
US-7,875,912 Zr.sub.x Hf.sub.y Sn.sub.1-x-y O.sub.2 films as high k gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) and tin oxide (SnO.sub.2)...
US-7,875,821 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,875,529 Semiconductor devices
Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for...
US-7,875,110 Electroless plating bath composition and method of use
An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An...
US-7,873,882 Circuits and methods for repairing defects in memory devices
Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The...
US-7,872,926 Input buffer and method with AC positive feedback, and a memory device and computer system using same
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative...
US-7,872,924 Multi-phase duty-cycle corrected clock signal generator and memory having same
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such...
US-7,872,923 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may...
US-7,872,920 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based...
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line...
US-7,872,912 M+N bit programming and M+L bit read for M bit memory cells
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage...
US-7,872,911 Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of...
US-7,872,682 Eclipse elimination by monitoring the pixel signal level
An anti-eclipse circuit for an imaging sensor monitors the photo signal level output by a pixel to determine whether the photo signal corresponds to the pixel...
US-7,872,676 Methods, systems, and devices for offset compensation in CMOC imagers
Methods, devices, and systems for offset compensation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of...
US-7,872,507 Delay lines, methods for delaying a signal, and delay lock loops
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of...
US-7,872,332 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and...
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system...
US-7,872,284 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,871,911 Methods for fabricating semiconductor device structures
Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may...
US-7,870,351 System, apparatus, and method for modifying the order of memory accesses
Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices....
US-7,870,330 Controller for refreshing memories
A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device...
US-7,870,329 System and method for optimizing interconnections of components in a multichip memory module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have...
US-7,869,494 Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI)...
US-7,869,457 High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
US-7,869,285 Low voltage operation bias current generation circuit
Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a...
US-7,869,249 Complementary bit PCRAM sense amplifier and method of operation
A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM...
US-7,869,242 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,868,630 Integrated light conditioning devices on a probe card for testing imaging devices, and methods of fabricating same
A probe card is disclosed which includes a body, at least one housing in the body, the housing having at least one light opening, and at least one light...
US-7,868,440 Packaged microdevices and methods for manufacturing packaged microdevices
Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the...
US-7,868,369 Localized masking for semiconductor structure development
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical...
US-7,868,310 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,867,919 Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a...
US-7,867,851 Methods of forming field effect transistors on substrates
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect...
US-7,867,850 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or...
US-7,867,845 Transistor gate forming methods and transistor structures
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill...
US-7,867,844 Methods of forming NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-7,865,659 Removable storage device
In an embodiment, when a removable storage device is removably coupled to a host, the removable storage device indicates that it is non-removable to the host....
US-7,865,009 Magnetic ink character reading apparatus
In the magnetic ink character reading apparatus, a first determination section reads signal data sequentially from a signal data string corresponding to the...
US-7,864,609 Methods for determining resistance of phase change memory elements
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of...
US-7,864,607 Negative voltage discharge scheme to improve snapback in a non-volatile memory
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge...
US-7,864,589 Mitigation of runaway programming of a memory device
Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided....
US-7,864,587 Programming a memory device to increase data reliability
Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed...
US-7,864,585 Multi level inhibit scheme
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions...
US-7,864,584 Expanded programming window for non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel...
US-7,864,577 Sharing physical memory locations in memory devices
A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of...
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