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Patent # Description
US-7,869,285 Low voltage operation bias current generation circuit
Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a...
US-7,869,249 Complementary bit PCRAM sense amplifier and method of operation
A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM...
US-7,869,242 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,868,630 Integrated light conditioning devices on a probe card for testing imaging devices, and methods of fabricating same
A probe card is disclosed which includes a body, at least one housing in the body, the housing having at least one light opening, and at least one light...
US-7,868,440 Packaged microdevices and methods for manufacturing packaged microdevices
Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the...
US-7,868,369 Localized masking for semiconductor structure development
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical...
US-7,868,310 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,867,919 Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a...
US-7,867,851 Methods of forming field effect transistors on substrates
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect...
US-7,867,850 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or...
US-7,867,845 Transistor gate forming methods and transistor structures
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill...
US-7,867,844 Methods of forming NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-7,865,659 Removable storage device
In an embodiment, when a removable storage device is removably coupled to a host, the removable storage device indicates that it is non-removable to the host....
US-7,865,009 Magnetic ink character reading apparatus
In the magnetic ink character reading apparatus, a first determination section reads signal data sequentially from a signal data string corresponding to the...
US-7,864,609 Methods for determining resistance of phase change memory elements
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of...
US-7,864,607 Negative voltage discharge scheme to improve snapback in a non-volatile memory
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge...
US-7,864,589 Mitigation of runaway programming of a memory device
Methods for mitigating runaway programming in a memory device, methods for program verifying a memory device, a memory device, and a memory system are provided....
US-7,864,587 Programming a memory device to increase data reliability
Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed...
US-7,864,585 Multi level inhibit scheme
Memory devices and methods are disclosed to facilitate utilization of a multi level inhibit programming scheme. In one such embodiment, isolated channel regions...
US-7,864,584 Expanded programming window for non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for utilizing an expanded programming window for non-volatile multilevel...
US-7,864,577 Sharing physical memory locations in memory devices
A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of...
US-7,864,575 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,864,457 Achromatic lens structure, method of fabrication, and imaging devices and systems using the same
Lens structures, imaging devices, and methods of making the same that include a lens and a transparent material having different dispersions and used to correct...
US-7,864,294 Focus sensitive lithographic apparatus, systems, and methods
A system includes an illuminator, a mask, and a measurement device. The illuminator includes a light source. The mask includes at least one focus determination...
US-7,863,924 Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using...
Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment...
US-7,863,727 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a...
US-7,863,722 Stackable semiconductor assemblies and methods of manufacturing such assemblies
Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor...
US-7,863,667 Zirconium titanium oxide films
Dielectric layers having an atomic layer deposited oxide containing titanium and zirconium and a method of fabricating such a dielectric layer produce a reliable...
US-7,863,663 Hybrid electrical contact
Techniques for manufacturing an electronic device. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A...
US-7,863,597 Resistance variable memory devices with passivating material
A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide...
US-7,863,595 Reproducible resistance variable insulating memory devices having a shaped bottom electrode
The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the...
US-7,863,199 Methods of forming particle-containing materials
The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials....
US-7,863,198 Method and device to vary growth rate of thin films over semiconductor structures
Methods and devices for controlling a growth rate of films in semiconductor structures are shown. Chemical vapor deposition methods and devices include the use...
US-7,863,187 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature...
US-7,863,176 Low-resistance interconnects and methods of making same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
US-7,863,133 Oxide epitaxial isolation
Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming...
US-7,862,964 Methods for photo-processing photo-imageable material
The invention includes methods for photo-processing photo-imageable material. Locations of the photo-imageable material where flare hot spots are expected to...
US-7,862,733 Method for manufacturing a probe
The present invention provides a probe manufacturing method in which, after a metal material for a probe is deposited on a base table, the probe can be detached...
US-7,862,316 Foamed mechanical planarization pads made with supercritical fluid
Foamed thermoplastic polymeric mechanical planarization polishing pads ("MP pads") made with supercritical fluids are presented. A supercritical fluid foaming...
US-7,862,232 Temperature sensor, device and system including same, and method of operation
A temperature sensor and device and system including same, comprise a switched capacitor circuit configured to generate a noise voltage in response to switching...
US-7,861,139 Programming management data for NAND memories
Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a...
US-7,860,294 Magnetic ink character reading apparatus and method of controlling the same
A magnetic ink character reading apparatus includes a similarity acquisition unit, a character recognition unit and a character recognition limiting unit. The...
US-7,859,922 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,859,916 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a...
US-7,859,893 Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
US-7,859,888 Resistive memory device
A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage...
US-7,859,295 Transmitter apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost...
US-7,859,282 Electrical connecting apparatus
An electrical connecting apparatus for use in electrical measurement of a device under test comprises a supporting member and a flat plate-like probe base plate....
US-7,859,112 Additional metal routing in semiconductor devices
Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate...
US-7,859,050 Memory having a vertical access device
Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a...
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