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Patent # Description
US-7,919,846 Stacked semiconductor component having through wire interconnect
A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on...
US-7,919,829 Liner for shallow trench isolation
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a...
US-7,919,800 Capacitor-less memory cells and cell arrays
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of...
US-7,919,386 Methods of forming pluralities of capacitors
The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a...
US-7,919,218 Method for a multiple exposure beams lithography tool
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by...
US-7,918,383 Methods for placing substrates in contact with molten solder
Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder...
US-7,917,962 BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
US-7,917,685 Method for reading a multilevel cell in a non-volatile memory device
A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell...
US-7,917,684 Bus translator
Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus...
US-7,917,479 Non-volatile memory devices, systems including same and associated methods
A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array...
US-7,916,557 NAND interface
A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a...
US-7,916,553 Memory system and method having volatile and non-volatile memory devices at same hierarchical level
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer...
US-7,916,546 Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply...
Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less...
US-7,916,544 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
US-7,916,543 Memory cell operation
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of...
US-7,916,536 Programming based on controller performance requirements
Methods and solid state drives are disclosed, including a solid state drive that is adapted to receive and transmit analog data signals representative of bit...
US-7,916,396 Lens master devices, lens structures, imaging devices, and methods and apparatuses of making the same
A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a...
US-7,916,204 Multiple microlens system for image sensors or display
An imager or display system with multiple lenses, which are formed, patterned and shaped over one or more pixels in an imager or display array. The multiple...
US-7,916,186 Anti-eclipse circuitry with tracking of floating diffusion reset level
An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent...
US-7,915,937 Circuitry and methods for improving differential signals that cross power domains
Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain...
US-7,915,924 Method and apparatus for selecting an operating mode based on a determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
US-7,915,916 Antifuse programming circuit with snapback select transistor
An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The...
US-7,915,736 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a...
US-7,915,735 Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
US-7,915,726 Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods...
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed...
US-7,915,718 Apparatus for flip-chip packaging providing testing capability
A method and apparatus for increasing the integrated circuit density in a flip-chip semiconductor device assembly including an interposer substrate facilitating...
US-7,915,711 Semiconductor assemblies and methods of manufacturing such assemblies including trenches in a molding material...
Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of...
US-7,915,692 Semiconductor structure including gateline surrounding source and drain pillars
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,915,673 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-7,915,669 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,915,659 Devices with cavity-defined gates and methods of making the same
A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a...
US-7,915,174 Dielectric stack containing lanthanum and hafnium
Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in...
US-7,915,168 Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
US-7,915,126 Methods of forming non-volatile memory cells, and methods of forming NAND cell unit string gates
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
US-7,915,116 Relaxed-pitch method of aligning active area to digit line
According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at...
US-7,915,077 Methods of making metal core foldover package structures
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked ...
US-7,913,062 Method of rotating data in a plurality of processing elements
A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the...
US-7,913,035 Method and apparatus for address FIFO for high bandwidth command/address busses in digital storage system
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a...
US-7,913,033 Non-volatile memory device having assignable network identification
Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The...
US-7,912,671 Method for measuring the position of a mark in a deflector system
The present invention relates to a method for determining the coordinates of an arbitrarily shaped pattern in a deflector system. The method basically comprises...
US-7,911,872 Column/row redundancy architecture using latches programmed from a look up table
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
US-7,911,865 Temperature compensation of memory signals using digital signals
A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates...
US-7,911,837 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,911,819 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of...
US-7,911,245 Multi-phase signal generator and method
A multi-phase signal generators and methods for generating multi-phase signals are described. In one embodiment, a clock generator generates quadrature signals...
US-7,910,972 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
US-7,910,971 Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the...
US-7,910,905 Self-aligned, planar phase change memory elements and devices
Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second...
US-7,910,660 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
US-7,910,487 Reverse masking profile improvements in high aspect ratio etch
A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of...
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