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Patent # Description
US-7,862,964 Methods for photo-processing photo-imageable material
The invention includes methods for photo-processing photo-imageable material. Locations of the photo-imageable material where flare hot spots are expected to...
US-7,862,733 Method for manufacturing a probe
The present invention provides a probe manufacturing method in which, after a metal material for a probe is deposited on a base table, the probe can be detached...
US-7,862,316 Foamed mechanical planarization pads made with supercritical fluid
Foamed thermoplastic polymeric mechanical planarization polishing pads ("MP pads") made with supercritical fluids are presented. A supercritical fluid foaming...
US-7,862,232 Temperature sensor, device and system including same, and method of operation
A temperature sensor and device and system including same, comprise a switched capacitor circuit configured to generate a noise voltage in response to switching...
US-7,861,139 Programming management data for NAND memories
Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a...
US-7,860,294 Magnetic ink character reading apparatus and method of controlling the same
A magnetic ink character reading apparatus includes a similarity acquisition unit, a character recognition unit and a character recognition limiting unit. The...
US-7,859,922 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,859,916 Symmetrically operating single-ended input buffer devices and methods
Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a...
US-7,859,893 Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or...
US-7,859,888 Resistive memory device
A device having a resistive memory element, a control device, a digit line and a sensing circuit. The sensing circuit is configured to sense a voltage...
US-7,859,295 Transmitter apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost...
US-7,859,282 Electrical connecting apparatus
An electrical connecting apparatus for use in electrical measurement of a device under test comprises a supporting member and a flat plate-like probe base plate....
US-7,859,112 Additional metal routing in semiconductor devices
Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate...
US-7,859,050 Memory having a vertical access device
Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a...
US-7,859,046 Ballistic direct injection NROM cell on strained silicon structures
A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the...
US-7,859,036 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form...
US-7,858,815 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds
A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,858,535 Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes and...
Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished...
US-7,858,523 Unsymmetrical ligand sources, reduced symmetry metal-containing compounds, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In some...
US-7,858,518 Method for forming a selective contact and local interconnect in situ
A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of...
US-7,858,506 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-7,858,486 Methods of forming a plurality of capacitors
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,858,471 Methods of fabricating an access transistor for an integrated circuit device, methods of fabricating periphery...
Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having...
US-7,858,468 Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant...
US-7,858,458 CMOS fabrication
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second...
US-7,858,420 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,857,982 Methods of etching features into substrates
The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A...
US-7,857,646 Electrical testing apparatus having masked sockets and associated systems and methods
An apparatus for forming a temporary electrical connection with a microelectronic component and associated systems and methods are disclosed herein. Embodiments...
US-7,856,888 Fiber optic strain gage and carrier
The current invention relates to optical gages designed to measure strain on the surface of a test specimen. The gages of this invention is designed to be...
US-7,855,931 Memory system and method using stacked memory device dice, and system using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is...
US-7,855,928 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,855,927 NAND system with a data write frequency greater than a command-and-address-load frequency
The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second...
US-7,855,922 Memory device bit line sensing system and method that compensates for bit line resistance variations
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit...
US-7,855,913 Dynamically configurable MLC state assignment
Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device...
US-7,855,585 Local coarse delay units
One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a...
US-7,855,462 Packaged semiconductor assemblies and methods for manufacturing such assemblies
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of...
US-7,855,454 Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate...
US-7,855,341 Methods and apparatus for a flexible circuit interposer
A substrate having a bending region and conductive paths formed therethrough is provided. In one embodiment, conductive paths are formed from a first region on...
US-7,855,154 Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer...
A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously...
US-7,855,148 Methods of isolating array features during pitch doubling processes and semiconductor device structures having...
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one...
US-7,855,140 Method of forming vias in semiconductor substrates and resulting structures
Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a...
US-7,855,085 System and method for reducing shorting in memory cells
An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce...
US-7,854,644 Systems and methods for removing microfeature workpiece surface defects
Systems and methods for removing microfeature workpiece surface defects are disclosed. A method for processing a microfeature workpiece in accordance with one...
US-7,853,841 Memory cell programming
Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One...
US-7,853,725 USB device communication apparatus, systems, and methods
Methods, systems and apparatus may operate to send and receive universal serial bus (USB) control endpoint standard device requests with embedded functional...
US-7,852,681 Non-volatile one time programmable memory
A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further...
US-7,852,671 Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide...
US-7,852,668 Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
US-7,852,658 Phase change memory cell with constriction structure
Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the...
US-7,852,385 Imager row-wise noise correction
An imager having optically and electrically black reference pixels in each row of the imager's pixel array. Since the reference pixels of each row experience the...
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