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Phase change material and methods of forming the phase change material
A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the...
Capacitors and methods with praseodymium oxide insulators
Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and...
Devices and systems having at least one dam structure
A method for forming through-wafer interconnects (TWI) in a substrate. Blind holes are formed from a surface, sidewalls thereof are passivated and coated with a...
Method of forming a field effect transistor
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one...
Methods for fabricating semiconductor components and packaged
Packaged semiconductor components and methods for manufacturing packaged semiconductor components. In one embodiment a semiconductor component comprises a die...
Recessed gate dielectric antifuse
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the...
Method of fabricating semiconductor components with through interconnects
A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate...
Methods for releasably attaching support members to microfeature
workpieces and microfeature assemblies formed...
Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods are disclosed herein. A method...
Systems and methods for compressing an encapsulant adjacent a
Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece are disclosed. A method in accordance with one aspect includes placing a...
Electron beam etching device and method
Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching...
Electrical connecting apparatus
An electrically connecting apparatus comprises a base member provided with slots penetrating in the plate thickness direction, contacts disposed within the slots...
JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
Distributed programmable priority encoder capable of finding the longest
match in a single operation
A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section...
Devices, systems, and methods for independent output drive strengths
Methods, apparatuses and systems are disclosed for independently configurable data and strobe drivers within a memory device. A memory device may include at...
Digital filters with memory
A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the...
Mitigation of data corruption from back pattern and program disturb in a
non-volatile memory device
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program...
Method and apparatus providing color interpolation in color filter arrays
using edge detection and correction terms
A method and apparatus for color plane interpolation are provided which interpolates the color values of pixels differently depending on an edge direction and...
Coupling cancellation scheme
Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of...
Partitioned through-layer via and associated systems and methods
Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a ...
Stackable ceramic FBGA for high thermal applications
An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor...
High permeability layered films to reduce noise in high speed
An apparatus provides a memory having a transmission line circuit with an associated high permeability material. The high permeability material may include a...
Microelectronic devices and methods for forming interconnects in
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
High density NAND non-volatile memory device
Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that...
Methods of forming capacitors, and methods of forming DRAM arrays
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
Taped semiconductor device and method of manufacture
Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously....
Method of forming pitch multipled contacts
Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching...
Electrical interconnect using locally conductive adhesive
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one...
Hybrid arithmetic logic unit
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a...
Devices and methods for a threshold voltage difference compensated sense
A voltage compensated sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to...
Precharge control circuits and methods for memory having buffered write
Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at...
Apparatus and method for increasing data line noise tolerance
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage,...
Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
Memory device with variable trim setting
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one...
Method to recover the exposure sensitivity of chemically amplified resins
from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
Exposure control for image sensors
An imaging system utilizes an exposure control circuit to control the length of an exposure in full frame mode. The exposure control circuit receives as an input...
Clock jitter compensated clock circuits and methods for generating jitter
compensated clock signals
Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive...
Integrated circuit comparator or amplifier
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
Memory cell with buried digit line
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of...
Array of capacitors with electrically insulative rings
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
Sacrificial self-aligned interconnect structures
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying...
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
Method of forming a thin film transistor
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
Methods of forming variable resistance memory cells, and methods of
etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
Die singulation methods
Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against...
Method of forming memory devices by performing halogen ion implantation
and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
Methods of forming a plurality of transistor gates, and methods of forming
a plurality of transistor gates...
A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a...
Methods of providing electrical isolation in semiconductor structures
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having...
DRAM arrays, vertical transistor structures, and methods of forming
transistor structures and DRAM arrays
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The...