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Patent # Description
US-7,825,462 Transistors
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-7,825,452 Memory cell with buried digit line
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of...
US-7,825,451 Array of capacitors with electrically insulative rings
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,825,450 Sacrificial self-aligned interconnect structures
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying...
US-7,825,443 Semiconductor constructions
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
US-7,825,414 Method of forming a thin film transistor
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
US-7,825,033 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
US-7,825,010 Die singulation methods
Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against...
US-7,824,994 Method of forming memory devices by performing halogen ion implantation and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-7,824,986 Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates...
A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a...
US-7,824,983 Methods of providing electrical isolation in semiconductor structures
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having...
US-7,824,982 DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The...
US-7,824,741 Method of forming a carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
US-7,824,505 Method to address carbon incorporation in an interpoly oxide
A method of removing a mask and addressing interfacial carbon chemisorbed in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip...
US-7,823,440 Systems and methods for characterizing thickness and topography of microelectronic workpiece layers
Metrology systems, tools, and methods that characterize one or more layers of a microelectronic workpiece are disclosed herein. In one embodiment, a system for...
US-7,823,024 Memory hub tester interface and method for use thereof
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a...
US-7,822,911 Memory device and method with on-board cache system for facilitating interface with multiple processors, and...
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a...
US-7,822,904 Capturing read data
Various techniques for capturing read data from a memory bus are disclosed herein. In one embodiment, a computing system includes a memory device, a memory bus...
US-7,822,076 Apparatus for multiplexing signals through I/O pins
One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor...
US-7,821,848 External clock tracking pipelined latch scheme
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data...
US-7,821,831 Block erase for volatile memory
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a...
US-7,821,830 Flash memory device with redundant columns
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns....
US-7,821,810 Phase change memory adaptive programming
Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed...
US-7,821,555 Multi path power for CMOS imagers
An analog signal chain for a CMOS active pixel sensor imaging system utilizes, for each amplification stage, a plurality of fixed gain amplifiers instead of a...
US-7,821,321 Semiconductor temperature sensor using bandgap generator circuit
A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators...
US-7,821,291 Digital calibration circuits, devices and systems including same, and methods of operation
A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a...
US-7,821,142 Intermediate semiconductor device structures
An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is...
US-7,821,108 Systems and methods for lowering interconnect capacitance through adjustment of relative signal levels
Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are...
US-7,821,107 Die stacking with an annular via having a recessed socket
A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety...
US-7,821,052 Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation...
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line...
US-7,821,048 Double density MRAM with planar processing
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-7,820,545 Methods of forming conductive interconnects
The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The...
US-7,820,506 Capacitors, dielectric structures, and methods of forming dielectric structures
Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may...
US-7,820,484 Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-7,820,459 Methods relating to the reconstruction of semiconductor wafers for wafer level processing including forming of...
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities...
US-7,819,672 Electrical connecting apparatus with inclined probe recess surfaces
An electrical connecting apparatus comprises a housing having a first recess extending in a first direction in a horizontal plane, opened downward, and having at...
US-7,819,668 Electrical connecting apparatus and method for manufacturing the same
The present invention provides an electrical connecting apparatus in which no strong stress acts on a coupling portion of an arm portion continuing into a base...
US-7,819,005 Sensor and transducer devices comprising carbon nanotubes, methods of making and using the same
Devices usable as sensors, as transducers, or as both sensors and transducers include one or more nanotubes or nanowires. In some embodiments, the devices may...
US-7,818,710 Method and system for lithographic simulation and verification
Methods and systems for lithographic simulation and verification comprising a process in the frequency domain or in the spatial domain of calculating intensity...
US-7,818,638 Systems and devices including memory with built-in self test and methods of making and using the same
Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module...
US-7,818,611 Memory device internal parameter reliability
Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and...
US-7,818,601 Method and apparatus for data transfer
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the...
US-7,818,027 Portable terminal and apparatus and method for driving the same
A portable terminal is capable of large screen display and includes an apparatus for driving the same. The portable terminal includes a first display panel unit...
US-7,817,874 Image sensor occlusion localization and correction apparatus, systems, and methods
Embodiments described herein may operate to illuminate an image sensor array (ISA) used in, for example, a digital imager alternately using a first illuminator...
US-7,817,483 Memory device having terminals for transferring multiple types of data
A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit...
US-7,817,478 Erase degradation reduction in non-volatile memory
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate...
US-7,817,467 Memory controller self-calibration for removing systemic influence
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each...
US-7,817,454 Variable resistance memory with lattice array using enclosing transistors
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is...
US-7,817,073 Integrators for delta-sigma modulators
Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory...
US-7,816,973 Devices and methods for reducing effects of device mismatch in temperature sensor circuits
A temperature sensor having one or more mirror circuits output temperature dependent output signals is disclosed in one embodiment. The temperature sensor...
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