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Patent # Description
US-7,898,337 High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital...
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one...
US-7,898,308 Apparatus and method for trimming static delay of a synchronizing circuit
A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals...
US-7,898,294 Pre-driver logic
At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives...
US-7,898,290 Method and apparatus for high resolution ZQ calibration
A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is...
US-7,898,064 Methods for forming through wafer interconnects and structures resulting therefrom
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
US-7,898,062 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,898,022 Scalable multi-functional and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two...
US-7,898,019 Semiconductor constructions having multiple patterned masking layers over NAND gate stacks
Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string...
US-7,898,017 Floating-gate memory cell and memory device and electronic system therewith
A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the...
US-7,898,010 Transparent conductor based pinned photodiode
A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region...
US-7,897,953 Multi-level programmable PCRAM memory
A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to...
US-7,897,751 Pharmaceutical preparation
A pharmaceutical preparation comprises nano-level particles (nanospheres) of a biocompatible polymer having, as held on their surfaces, an NF.kappa.B decoy...
US-7,897,517 Method of selectively depositing materials on a substrate using a supercritical fluid
A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a...
US-7,897,485 Wafer processing including forming trench rows and columns at least one of which has a different width
Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a...
US-7,897,470 Non-volatile memory cell device and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the...
US-7,897,465 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-7,897,460 Methods of forming recessed access devices associated with semiconductor constructions
The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the...
US-7,896,545 Apparatus and methods for temperature calibration and sensing
Some embodiments include apparatus and methods having a first switch, a second switch, and a circuit coupled to the first and second switches. The first switch...
US-7,895,485 System and method for testing a packetized memory device
Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator...
US-7,895,479 System and method for initializing a memory system, and memory device and processor-based system using same
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory...
US-7,894,289 Memory system and method using partial ECC to achieve low power refresh and fast access to data
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first...
US-7,894,286 Array sense amplifiers, memory devices and systems including same, and methods of operation
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output ("I/O") node and a second...
US-7,894,285 Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations...
Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations....
US-7,894,271 Sensing of memory cells in a solid state memory device by fixed discharge of a bit line
In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to...
US-7,894,264 Controlling a memory device responsive to degradation
Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems...
US-7,892,978 Electron induced chemical etching for device level diagnosis
A method of imaging and identifying materials, contamination, fabrication errors, and defects on and below the surface of an integrated circuit (IC) is...
US-7,892,972 Methods for fabricating and filling conductive vias and conductive vias so formed
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers,...
US-7,892,964 Vapor deposition methods for forming a metal-containing layer on a substrate
Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as...
US-7,892,943 Isolation trenches for memory devices
A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug...
US-7,892,942 Methods of forming semiconductor constructions, and methods of forming isolation regions
Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing...
US-7,892,941 Technique for forming shallow trench isolation structure without corner exposure
A shallow isolation trench structure and methods of forming the same wherein the method of formation comprises a layered structure of a buffer film layer over a...
US-7,892,937 Methods of forming capacitors
Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of...
US-7,892,921 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate...
US-7,890,819 Method and apparatus for storing failing part locations in a module
A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module,...
US-7,889,562 Adjusting programming or erase voltage pulses in response to a rate of programming or erasing
Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to...
US-7,889,561 Read operation for NAND memory
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively...
US-7,888,991 Clock distribution network
Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide...
US-7,888,958 Current test probe having a solder guide portion, and related probe assembly and production method
A probe for current test is provided. The probe includes a probe body having a plate-like connection portion whose end face becomes a connection face to a probe...
US-7,888,774 Interconnect line selectively isolated from an underlying contact plug
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and...
US-7,888,744 Strained semiconductor, devices and systems and methods of formation
In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The...
US-7,888,721 Surround gate access transistors with grown ultra-thin bodies
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid...
US-7,888,255 Method of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry
A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through...
US-7,888,188 Method of fabicating a microelectronic die having a curved surface
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a...
US-7,888,185 Semiconductor device assemblies and systems including at least one conductive pathway extending around a side...
Semiconductor device assemblies and systems that include at least one semiconductor device assembly include two or more semiconductor devices stacked one over...
US-7,888,165 Methods of forming a phase change material
Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias...
US-7,885,782 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed...
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is...
US-7,885,128 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-7,884,630 IC carrie, IC socket and method for testing IC device
An IC device (10) held on an IC carrier (24) is a double-sided electrode type BGA IC device (10) provided with bump electrodes (14) on a first surface of a...
US-7,884,629 Probe card layout
Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater efficiency during testing of a substrate having a plurality of die...
US-7,884,405 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
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