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Patent # Description
US-7,813,192 System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
US-7,813,167 Memory cell
Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell...
US-7,812,657 Methods and apparatus for synchronizing with a clock signal
Clock synchronization and skew adjustment circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time...
US-7,812,652 Locked loops, bias generators, charge pumps and methods for generating control voltages
Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for...
US-7,812,593 Method for improving stability and lock time for synchronous circuits
Delay-locked loops, signal locking methods and devices incorporating delay-locked loops are described. A delay-locked loop includes a forward loop path, a...
US-7,812,461 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose...
US-7,812,447 Wafer level pre-packaged flip chip
A pre-packaged flip chip package that includes one or more dice on a semiconductor wafer is disclosed. In the various embodiments, an adhesive layer may be...
US-7,812,436 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,812,334 Phase change memory elements using self-aligned phase change material layers and methods of making and using same
A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material...
US-7,811,940 Topography directed patterning
A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises...
US-7,811,935 Isolation regions and their formation
A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the...
US-7,811,903 Thin flip-chip method
Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of...
US-7,811,897 Method of forming trench isolation
A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed...
US-7,811,840 Diodes, and methods of forming diodes
Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over...
US-7,810,017 Variable sector-count ECC
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by...
US-7,809,901 Combined parallel/serial status register read
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined...
US-7,809,519 System and method for automatically calibrating a temperature sensor
There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system made up of a temperature...
US-7,808,824 Interleaved memory program and verify method, device and system
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The...
US-7,808,648 Method and device for optical determination of physical properties of features, not much larger than the...
A method and device for optical determination of physical properties of features, not much larger than the optical wavelength used, on a test sample are...
US-7,808,289 Method and apparatus for digital phase generation for high frequency clock applications
An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal....
US-7,808,112 Wafer level pre-packaged flip chip system
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment,...
US-7,808,063 Structure and method for FPN reduction in imaging devices
Imaging devices having reduced fixed pattern noise are disclosed. The fixed pattern noise in the imaging devices is reduced by measuring and adjusting the...
US-7,808,042 Systems and devices including multi-gate transistors and methods of using, making, and operating the same
Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit...
US-7,808,041 Semiconductor constructions of memory device with different depth gate line trenches
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.8. The recessed...
US-7,807,582 Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a...
US-7,807,575 Methods to reduce the critical dimension of semiconductor devices
A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of...
US-7,807,541 Concentric or nested container capacitor structure for integrated circuits
Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made...
US-7,807,535 Methods of forming layers comprising epitaxial silicon
The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over...
US-7,807,505 Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging...
US-7,807,503 Die-wafer package and method of fabricating same
A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a...
US-7,807,502 Method for fabricating semiconductor packages with discrete components
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,807,062 Electron induced chemical etching and deposition for local circuit repair
A method of imaging and repairing defects on and below the surface of an integrated circuit (IC) is described. The method may be used in areas as small as one...
US-7,806,988 Method to address carbon incorporation in an interpoly oxide
A method of removing a mask and addressing interfacial carbon chemisbored in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip...
US-7,806,449 Substrate pick
A device for handling devices, such as reticles, in a semiconductor manufacturing environment. In one illustrative embodiment, the device includes a body, a...
US-7,805,694 Apparatus and method to facilitate hierarchical netlist checking
An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification...
US-7,805,586 System and method for optimizing interconnections of memory devices in a multichip module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the...
US-7,805,561 Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random...
US-7,804,525 Method, apparatus, and system for selecting pixels for automatic white balance processing
A method, apparatus, and system that use a white balance operation. A selecting process is applied to each pixel selected and considered for automatic white...
US-7,804,344 Periodic signal synchronization apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a...
US-7,804,324 Dynamically adjusting operation of a circuit within a semiconductor device
Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device...
US-7,804,171 Techniques for packaging a multiple device component
A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip...
US-7,804,168 Ball grid array structures having tape-based circuitry
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using...
US-7,804,144 Low-temperature grown high quality ultra-thin CoTiO.sub.3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,804,139 Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench
Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide....
US-7,804,115 Semiconductor constructions having antireflective portions
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
US-7,803,686 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-7,802,157 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal...
US-7,800,965 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,800,953 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile...
A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the...
US-7,800,947 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
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