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Patent # Description
US-7,809,901 Combined parallel/serial status register read
Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined...
US-7,809,519 System and method for automatically calibrating a temperature sensor
There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system made up of a temperature...
US-7,808,824 Interleaved memory program and verify method, device and system
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The...
US-7,808,648 Method and device for optical determination of physical properties of features, not much larger than the...
A method and device for optical determination of physical properties of features, not much larger than the optical wavelength used, on a test sample are...
US-7,808,289 Method and apparatus for digital phase generation for high frequency clock applications
An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal....
US-7,808,112 Wafer level pre-packaged flip chip system
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment,...
US-7,808,063 Structure and method for FPN reduction in imaging devices
Imaging devices having reduced fixed pattern noise are disclosed. The fixed pattern noise in the imaging devices is reduced by measuring and adjusting the...
US-7,808,042 Systems and devices including multi-gate transistors and methods of using, making, and operating the same
Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit...
US-7,808,041 Semiconductor constructions of memory device with different depth gate line trenches
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.8. The recessed...
US-7,807,582 Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a...
US-7,807,575 Methods to reduce the critical dimension of semiconductor devices
A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of...
US-7,807,541 Concentric or nested container capacitor structure for integrated circuits
Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made...
US-7,807,535 Methods of forming layers comprising epitaxial silicon
The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over...
US-7,807,505 Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging...
US-7,807,503 Die-wafer package and method of fabricating same
A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a...
US-7,807,502 Method for fabricating semiconductor packages with discrete components
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,807,062 Electron induced chemical etching and deposition for local circuit repair
A method of imaging and repairing defects on and below the surface of an integrated circuit (IC) is described. The method may be used in areas as small as one...
US-7,806,988 Method to address carbon incorporation in an interpoly oxide
A method of removing a mask and addressing interfacial carbon chemisbored in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip...
US-7,806,449 Substrate pick
A device for handling devices, such as reticles, in a semiconductor manufacturing environment. In one illustrative embodiment, the device includes a body, a...
US-7,805,694 Apparatus and method to facilitate hierarchical netlist checking
An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification...
US-7,805,586 System and method for optimizing interconnections of memory devices in a multichip module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the...
US-7,805,561 Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random...
US-7,804,525 Method, apparatus, and system for selecting pixels for automatic white balance processing
A method, apparatus, and system that use a white balance operation. A selecting process is applied to each pixel selected and considered for automatic white...
US-7,804,344 Periodic signal synchronization apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a...
US-7,804,324 Dynamically adjusting operation of a circuit within a semiconductor device
Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device...
US-7,804,171 Techniques for packaging a multiple device component
A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip...
US-7,804,168 Ball grid array structures having tape-based circuitry
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using...
US-7,804,144 Low-temperature grown high quality ultra-thin CoTiO.sub.3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,804,139 Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench
Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide....
US-7,804,115 Semiconductor constructions having antireflective portions
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
US-7,803,686 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-7,802,157 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal...
US-7,800,965 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,800,953 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile...
A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the...
US-7,800,947 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,800,815 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,800,657 Method, apparatus and system using hierarchical histogram for automatic exposure adjustment of an image
A method, apparatus and system with a hierarchical histogram generator that generates sub-histograms of differing resolutions. These sub-histograms are used to...
US-7,800,384 Probe unit substrate
A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the...
US-7,800,238 Surface depressions for die-to-die interconnects and associated systems and methods
Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of...
US-7,800,137 Semiconductor constructions
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a...
US-7,800,092 Phase change memory elements using energy conversion layers, memory arrays and systems including same, and...
A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second...
US-7,800,042 Method and apparatus for setting black level in an imager using both optically black and tied pixels
An imaging pixel array includes an active area of pixels, organized into rows and columns of pixels. The array also includes a plurality of dark pixel columns...
US-7,800,001 Probe sheet and electrical connecting apparatus
An embodiment of a probe sheet enabling to restrict misalignment of the posture of each contactor accurately positioned on a probe sheet main body caused by...
US-7,799,694 Methods of forming semiconductor constructions
The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor...
US-7,799,610 Method of fabricating a stacked die having a recess in a die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided.
US-7,799,196 Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
US-7,799,180 Silver selenide sputtered films and method and apparatus for controlling defect formation in silver selenide...
Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A...
US-7,797,597 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating...
US-7,796,414 Memory module, system and method of making same
A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices...
US-7,795,934 Switched capacitor for a tunable delay circuit
A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a...
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