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Patent # Description
US-7,851,309 Selective epitaxy vertical integrated circuit components and methods
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are...
US-7,851,307 Method of forming complex oxide nanodots for a charge trap
Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is...
US-7,851,301 Semiconductor capacitor structure and method to form same
A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride...
US-7,851,292 Methods of forming and programming floating-gate memory cells having carbon nanotubes
Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into...
US-7,851,266 Microelectronic device wafers including an in-situ molded adhesive, molds for in-situ molding adhesives on...
A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing...
US-7,849,276 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-7,848,569 Method and apparatus providing automatic color balancing for digital imaging systems
Pixels from an image are sampled for gray world statistics. To avoid the effect of saturated regions, the pixels are pruned. If a predetermined percentage of the...
US-7,848,457 Constant delay zero standby differential logic receiver and method
A differential receiver circuit on an integrated circuit consumes substantially no standby power, has constant propagation delay regardless of the input common...
US-7,848,158 Methods and apparatuses for programming flash memory using modulated pulses
Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. An apparatus may have a pulse...
US-7,848,142 Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number...
US-7,847,626 Structure and method for coupling signals to and/or from stacked semiconductor dies
Signals are coupled to and from stacked semiconductor dies through first and second sets of external terminals. The external terminals in the second set are...
US-7,847,366 Well for CMOS imager
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically...
US-7,847,344 Memory utilizing oxide-nitride nanolaminates
Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain...
US-7,847,282 Vertical tunneling transistor
The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an...
US-7,846,851 Method and apparatus for a two-step resist soft bake to prevent ILD outgassing during semiconductor processing
A semiconductor wafer having no photoresist craters at the completion of a two-step post-apply resist bake (soft bake) in the fabrication of an integrated...
US-7,846,812 Methods of forming trench isolation and methods of forming floating gate transistors
A method of forming trench isolation includes etching first trench lines into semiconductive material of a semiconductor substrate. First isolation material is...
US-7,846,798 Methods of forming vertical transistor structures
The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical...
US-7,846,776 Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature...
Methods for releasably attaching sacrificial support members to microfeature workpieces and microfeature devices formed using such methods are disclosed herein....
US-7,846,768 Stacked die package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,846,623 Resist pattern and reflow technology
A reflow stabilizing solution for treating photoresist patterns and a reflow technology are disclosed. The reflow stabilizing solution comprises a polymer and is...
US-7,846,288 Methods and systems for removing protective films from microfeature workpieces
Methods and systems for removing protective films from microfeature workpieces are disclosed herein. One particular embodiment of such a method comprises...
US-7,845,540 Systems and methods for depositing conductive material into openings in microfeature workpieces
Systems and methods for depositing conductive material into openings in microfeature workpieces are disclosed herein. One particular embodiment of a system for...
US-7,844,811 Using chip select to specify boot memory
A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is...
US-7,844,142 Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures,...
Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data...
US-7,844,137 Multisampling with reduced bit samples
A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample from...
US-7,843,735 Sensing memory cells
Methods, devices, modules, and systems for operating memory cells are taught. A method for operating memory cells includes programming at least one of the memory...
US-7,843,726 Sensing against a reference cell
Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals...
US-7,843,725 M+L bit read column architecture for M bit memory cells
A memory device and programming and/or reading process is described that programs a row of non-volatile multi-level memory cells (MLC) in a single program...
US-7,843,204 Electrical connecting apparatus
The object of the present invention is to prevent an operator from touching electronic elements arranged on an upper surface of a probe assembly of an electrical...
US-7,843,198 Electrical connecting apparatus
An electrical connecting apparatus for use in an electrical inspection of a tester and a device under test. The electrical connecting apparatus is provided with...
US-7,843,050 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-7,842,926 Method and device for correcting SLM stamp image imperfections
The invention relates to production and precision patterning of work pieces, including manufacture of photomask for photolithography and direct writing on other...
US-7,842,915 Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including...
US-7,842,558 Masking process for simultaneously patterning separate regions
According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a...
US-7,842,525 Method and apparatus for personalization of semiconductor
A system for making small modifications to the pattern in standard processed semiconductor devices. The modifications are made to create a small variable part of...
US-7,842,523 Buried conductor for imagers
A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A...
US-7,840,952 Method and system for generating object code to facilitate predictive memory retrieval
A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references...
US-7,839,703 Subtraction circuits and digital-to-analog converters for semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
US-7,839,179 Balanced phase detector
Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of...
US-7,838,920 Trench memory structures and operation
Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various...
US-7,838,381 Stud capacitor device and fabrication method
The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in...
US-7,838,362 Method of making an embedded trap direct tunnel non-volatile memory
The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over...
US-7,838,360 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-7,838,183 Multi-layer, attenuated phase-shifting mask
The present invention provides an attenuated phase shift mask ("APSM") that, in each embodiment, includes completely transmissive regions sized and shaped to...
US-7,838,178 Masks for microlithography and methods of making and using such masks
Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on...
US-7,838,084 Atomic layer deposition method of depositing an oxide on a substrate
The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a...
US-7,837,889 Methods of etching nanodots, methods of removing nanodots from substrates, methods of fabricating integrated...
Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated...
US-7,837,805 Methods for treating surfaces
Some embodiments include methods of treating surfaces with aerosol particles. The aerosol particles may be formed as liquid particles, and then passed through a...
US-7,837,797 Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition
A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use...
US-7,836,374 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
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