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Patent # Description
US-1,014,1508 Clamp elements for phase change memory arrays
Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a...
US-1,014,1330 Methods of forming semiconductor device structures, and related semiconductor device structures, semiconductor...
A method of forming a semiconductor device structure comprises forming a stack structure comprising stacked tiers. Each of the stacked tiers comprises a first...
US-1,014,1314 Memories and methods to provide configuration information to controllers
A memory system includes a memory controller and a memory module coupled to the memory controller. One such memory module may include a memory package of a...
US-1,014,1262 Electrically conductive laminate structures
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
US-1,014,1259 Semiconductor devices having electrically and optically conductive vias, and associated systems and methods
Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a...
US-1,014,0225 Impedance adjustment in a memory device
Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the...
US-1,014,0222 Interface components
In an example, an apparatus may have a controller to be coupled to a host, an interface component coupled to the controller, and a plurality of memory devices...
US-1,014,0104 Target architecture determination
Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of...
US-1,014,0057 Apparatuses and methods for multiple address registers for a solid state device
The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus...
US-1,014,0040 Memory device with dynamic program-verify voltage calibration
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to:...
US-1,013,7481 Methods of removing particles from over semiconductor substrates
Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the...
US-1,013,7384 Systems and methods for water desalinization
An apparatus includes a set of atomizers, a housing and a separator. Each atomizer includes an inlet portion that receives an inlet flow of a solution and an...
US-1,013,5465 Error correction methods and apparatuses using first and second decoders
Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide...
US-1,013,4982 Array of cross point memory cells
An array of cross point memory cells comprises spaced first lines which cross spaced second lines. Two memory cells are individually between one of two...
US-1,013,4978 Magnetic cell structures, and methods of fabrication
A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a...
US-1,013,4969 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-1,013,4968 Solid state lighting devices with improved contacts and associated methods of manufacturing
Solid state lighting ("SSL") devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device...
US-1,013,4916 Transistor devices, memory cells, and arrays of memory cells
A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate...
US-1,013,4810 Three dimensional memory array with select device
Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a...
US-1,013,4798 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-1,013,4742 Semiconductor device including a semiconductor substrate, a pillar, and a beam
The semiconductor storage device includes a lower electrode that are vertically extended from a semiconductor substrate, a beam including a first portion...
US-1,013,4741 Methods of forming an elevationally extending conductor laterally between a pair of conductive lines
A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from...
US-1,013,4738 Low power memory device with JFET device structures
There is provided a low power memory device with JFET device structures. Specifically, a low power memory device is provided that includes a plurality memory...
US-1,013,4712 Methods and systems for improving power delivery and signaling in stacked semiconductor devices
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the...
US-1,013,4671 3D interconnect multi-die inductors with through-substrate via cores
A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV)...
US-1,013,4655 Semiconductor device packages with direct electrical connections and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An...
US-1,013,4647 Methods for forming interconnect assemblies with probed bond pads
An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The...
US-1,013,4597 Apparatuses including memory cells with gaps comprising low dielectric constant materials
Various embodiments include apparatuses and electronic devices. One such apparatus can include a first dielectric material and a second dielectric material, and...
US-1,013,4482 Apparatuses and methods for high speed writing test mode for memories
Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a...
US-1,013,4481 Pre-compensation of memory threshold voltage
Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target...
US-1,013,4478 Apparatuses and methods for reducing read disturb
Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate...
US-1,013,4470 Apparatuses and methods including memory and operation of same
Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying...
US-1,013,4461 Apparatuses and methods for selective row refreshes
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control...
US-1,013,4454 Apparatuses, circuits, and methods for biasing signal lines
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled...
US-1,013,4453 Invert operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,013,3628 Apparatuses and methods for encoding using error protection codes
The present disclosure relates to apparatuses and method for encoding using error protection codes. An example apparatus comprises circuitry, for instance,...
US-1,012,8916 Wireless communication link using near field coupling
A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field...
US-1,012,8847 Apparatuses and methods for level shifting
Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first...
US-1,012,8843 Apparatuses and methods for partial bit de-emphasis
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes...
US-1,012,8842 Output impedance calibration for signaling
Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated...
US-1,012,8802 Semiconductor device including amplifier
Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge...
US-1,012,8437 Semiconductor structures including memory materials substantially encapsulated with dielectric materials, and...
A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first...
US-1,012,8315 Methods of forming phase change memory apparatuses
Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the...
US-1,012,8265 Memory cells, integrated structures and memory arrays
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a...
US-1,012,8229 Semiconductor devices with package-level configurability
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first...
US-1,012,8217 Memory devices with controllers under memory packages and associated systems and methods
Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a...
US-1,012,8212 Semiconductor package and fabrication method thereof
A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be...
US-1,012,8183 Structure of integrated circuitry and a method of forming a conductive via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically...
US-1,012,8142 Semiconductor structures including carrier wafers and attached device wafers, and methods of forming such...
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars...
US-1,012,7994 Systems and methods for threshold voltage modification and detection
A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one...
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