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Patent # Description
US-9,524,248 Memory management for a hierarchical memory system
Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual...
US-9,524,207 Lee metric error correcting code
A memory device may include memory components for storing data. The memory device may also include a controller that determines whether one or more errors exist...
US-9,524,118 Systems, devices, memory controllers, and methods for controlling memory
Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device;...
US-9,524,117 Control of page access in memory
The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several...
US-9,522,270 Circuit for an implantable device
An integrated circuit includes: a radio-frequency (RF) to direct current (DC) rectifying circuit coupled to one or more antenna on an implantable wirelessly...
US-9,520,558 Semiconductor structures and memory cells including conductive material and methods of fabrication
Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first...
US-9,520,554 Clamp elements for phase change memory arrays
Clamp elements, memories, apparatuses, and methods for forming the same are disclosed herein. An example memory may include an array of memory cells and a...
US-9,520,553 Methods of forming a magnetic electrode of a magnetic tunnel junction and methods of forming a magnetic tunnel...
A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic MgO-comprising material over conductive material of the...
US-9,520,478 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,520,447 Memory cells having a common gate terminal
Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells...
US-9,520,370 Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor...
A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the...
US-9,520,190 Modified reset state for enhanced read margin of phase change memory
Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase...
US-9,520,183 Threshold voltage compensation in a memory
Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the...
US-9,520,176 Semiconductor memory device including power supply line
A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock...
US-9,520,170 Volume select for affecting a state of a non-selected memory volume
Apparatuses and methods of operating memory are described. One such method can include receiving a select command at a plurality of memory volumes of a memory...
US-9,519,860 Programmable device, hierarchical parallel machines, and methods for providing state information
Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable...
US-9,519,582 Sense operation flags in a memory device
Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines...
US-9,518,876 Method and measuring system for determining deformations of a geometric body with the aid of force measuring...
A method for ascertaining deformations of a geometric body or for measuring forces or torques acting thereon using force measuring sensors or deformation...
US-9,515,636 Apparatuses and methods for duty cycle adjustments
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of gates coupled together in series. A first pull-down circuit can be...
US-9,515,261 Memory cells and methods of making memory cells
Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a...
US-9,515,151 Gettering agents in memory charge storage structures
Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing...
US-9,515,046 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-9,515,002 Bonding pads with thermal pathways
Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal...
US-9,514,976 Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined...
US-9,514,975 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-9,514,905 Fuses, and methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
US-9,514,838 Apparatus including memory system controllers and related methods for memory management using block tables
Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control...
US-9,514,829 Access line management in a memory device
Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device...
US-9,514,809 Memory array plane select
Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged...
US-9,514,063 Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
US-9,513,992 Method and apparatus to perform concurrent read and write memory operations
Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a...
US-9,513,912 Memory controllers
Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one...
US-9,509,535 Multi-level signaling
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
US-9,509,312 Boolean logic in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic...
US-9,508,931 Memory cells and methods of forming memory cells
Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the...
US-9,508,735 Methods and apparatuses having strings of memory cells and select gates with double gates
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front...
US-9,508,686 Semiconductor device assembly with package interconnect extending into overlying spacer material, and...
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material...
US-9,508,628 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a...
US-9,508,591 Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a...
US-9,508,440 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-9,508,427 Apparatuses and methods including supply current in memory
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the...
US-9,508,426 Program-disturb management for phase change memory
Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a...
US-9,508,417 Methods and apparatuses for controlling timing paths and latency based on a loop delay
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An...
US-9,508,409 Apparatuses and methods for implementing masked write commands
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and...
US-9,508,407 Wiring configuration of a bus system and power wires in a memory chip
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective...
US-9,507,104 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,503,066 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-9,503,019 Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
US-9,502,650 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,502,642 Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
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