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Patent # Description
US-9,910,594 Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access...
Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include...
US-9,910,089 Inspection unit, probe card, inspection device, and control system for inspection device
An inspection unit in which a probe card is united with a connection body via a vacuum chamber. It prevents flatness of tips of probes provided on the probe...
US-9,908,731 Paper conveying mechanism for printing apparatus
A paper conveying mechanism includes an elastic urging member provided on each side surface of an upper guide. The urging member includes a projecting portion...
US-9,907,950 System and method for stimulation with electrode
Some implementations provide a method for modulating excitable tissue in a body of a patient, the method including: placing a wireless implantable stimulator...
US-9,905,279 Systems, circuits, and methods for charge sharing
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
US-9,904,515 Multiplication operations in memory
Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example...
US-9,899,070 Modified decode for corner turn
Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an...
US-9,898,252 Multiplication operations in memory
Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing...
US-9,895,692 Sample-to-answer microfluidic cartridge
A microfluidic cartridge and methods for performing a diagnostic, molecular or biochemical assay thereon, where all dried and/or liquid reagents necessary for...
US-9,893,723 Apparatuses and methods for reducing off state leakage currents
Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an...
US-9,893,282 Methods of forming resistive memory elements
A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising...
US-9,893,279 Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
US-9,893,277 Memory arrays and methods of forming memory cells
Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is...
US-9,893,083 Elevationally-extending strings of memory cells individually comprising a programmable charge storage...
A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the...
US-9,893,072 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-9,892,797 Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
US-9,892,784 Semiconductor device and error correction method
A device with error correction is provided. The device includes a plurality of memory cells, and reference read write circuit, a plurality of sense amplifiers,...
US-9,892,780 Semiconductor memory device including output buffer
An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power...
US-9,892,777 Cell-based reference voltage generation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first...
US-9,892,776 Half density ferroelectric memory and operation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory array may be operated in a half density mode, in which...
US-9,892,770 Methods and apparatuses for command shifter reduction
Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit,...
US-9,892,767 Data gathering in memory
Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of...
US-9,892,766 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,891,864 Non-volatile memory module architecture to support memory error correction
Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first...
US-9,891,842 Searching data in parallel using processor-in-memory devices
A method includes comparing, in parallel, a data pattern with data stored into a plurality of columns of memory cells, and in response to detecting the data...
US-9,888,574 Apparatus and methods for via connection with reduced via currents
Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first...
US-9,887,239 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-9,887,204 Memory cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
US-9,887,083 Methods of forming capacitors
A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner...
US-9,887,077 Removal of metal
Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing...
US-9,886,991 Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated...
Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM)...
US-9,886,017 Counter operation in a state machine lattice
Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting...
US-9,885,827 Apparatuses and methods for photonic communication and photonic addressing
Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources,...
US-9,882,016 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,882,015 Transistors, semiconductor devices, and electronic devices including transistor gates with conductive elements...
A method for fabricating a transistor gate with a conductive element that includes cobalt silicide includes use of a sacrificial material as a place-holder...
US-9,881,972 Array of memory cells and methods of forming an array of memory cells
A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive...
US-9,881,971 Memory arrays
Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense...
US-9,881,932 Methods of adjusting flatband voltage of a memory device
Methods for adjusting a flatband voltage of a memory device, including applying a voltage to a control gate of the memory device such that charged species are...
US-9,881,924 Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and...
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas...
US-9,881,923 Floating body transistors and memory arrays comprising floating body transistors
Some embodiments include a floating body transistor which has a gate structure configured as a bracket having two upwardly-projecting sidewalls joined to a...
US-9,881,910 Apparatuses and methods for forming die stacks
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base...
US-9,881,886 Semiconductor device assemblies including intermetallic compound interconnect structures
A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the...
US-9,881,858 Solder bond site including an opening with discontinuous profile
Apparatuses and methods for formation of a bond site including an opening with a discontinuous profile are disclosed herein. An example apparatus may at least...
US-9,881,786 Methods of forming nanostructures using self-assembled nucleic acids, and nanostructures thereof
A method of forming a nanostructure comprises forming a directed self-assembly of nucleic acid structures on a patterned substrate. The patterned substrate...
US-9,881,693 Selectors on interface die for memory device
Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that...
US-9,881,686 Apparatuses and methods to control body potential in 3D non-volatile memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
US-9,881,674 Sequential write and sequential write verify in memory device
Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory...
US-9,881,673 Memories having a shared resistance variable material
Memories having a plurality of resistive storage elements in a shared resistance variable material, a plurality of select devices coupled to the plurality of...
US-9,881,665 Semiconductor memory device including output buffer
An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power...
US-9,881,661 Charge mirror-based sensing for ferroelectric memory
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a...
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