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Analog sensing of memory cells with a source follower driver in a
semiconductor memory device
Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One...
Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful...
Programming sequence in NAND memory
An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source...
NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
MEM suspended gate non-volatile memory
A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing...
Dielectric relaxation memory
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site...
Packaged semiconductor components having substantially rigid support
members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of...
NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
Metal-substituted transistor gates
One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over...
Doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
Microelectronic workpieces and methods and systems for forming
interconnects in microelectronic workpieces
Methods and systems for forming electrical interconnects through microelectronic workpieces are disclosed herein. One aspect of the invention is directed to a...
Methods of fluxless micro-piercing of solder balls, and resulting devices
A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material,...
Semiconductor processing methods, methods of forming contact pads, and
methods of forming electrical...
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel...
Packaged microelectronic devices and methods for manufacturing packaged
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes...
ALD of silicon films on germanium
The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a...
Method for forming a self-aligned T-shaped isolation trench
The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical...
Methods of selectively oxidizing semiconductor structures, and structures
Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas...
Band-engineered multi-gated non-volatile memory device with enhanced
Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate...
High coupling memory cell
A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric...
Stacked microelectronic devices and methods for manufacturing
Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can...
Methods of forming imager systems
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
Method for adjusting dimensions of photomask features
A method for adjusting one or more dimensions of a photomask subsequent to etching of a defective pattern in the chrome-containing layer thereof is provided. The...
Methods and systems for releasably attaching support members to
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
Methods for treating surfaces
Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer...
Method and apparatus for detecting communication errors on a bus
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on...
Error correction for memory
Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing...
Method and apparatus of high-speed input sampling
A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and...
Scan line to block re-ordering buffer for image compression
A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing...
Method and system for generating reference voltages for signal receivers
A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In...
Techniques for reducing leakage current in memory devices
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus...
Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
Semiconductor memory device having bit line pre-charge unit separated from
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more...
NAND architecture memory devices and operation
Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit...
Methods and apparatus utilizing predicted coupling effect in the
programming of non-volatile memory
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized...
Wide dynamic range active pixel with knee response
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment a pixel circuit comprises a...
Class AB amplifier and imagers and systems using same
A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common...
Microelectronic devices having intermediate contacts for connection to
interposer substrates, and associated...
Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed...
Die package and probe card structures and fabrication methods
A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one...
Integrated circuit and seed layers
Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit....
Packaged microelectronic devices and methods for manufacturing packaged
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
Method and apparatus providing refractive index structure for a device
capturing or displaying images
A transient index stack having an intermediate transient index layer, for use in an imaging device or a display device, that reduces reflection between layers...
Ultra-thin body vertical tunneling transistor
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on...
Differential negative resistance memory
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes...
System and method for fabricating a fin field effect transistor
There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising...
Methods of forming memory cells
Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are...
Method of fabricating memory transistor
A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At...
Resistive memory cell fabrication methods and devices
A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom...
Defective memory block remapping method and system, and memory device and
processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output...
Method and apparatus for improving storage performance using a background
Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of...