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Patent # Description
US-7,830,718 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program...
US-7,830,426 Method and apparatus providing color interpolation in color filter arrays using edge detection and correction terms
A method and apparatus for color plane interpolation are provided which interpolates the color values of pixels differently depending on an edge direction and...
US-7,830,221 Coupling cancellation scheme
Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of...
US-7,830,018 Partitioned through-layer via and associated systems and methods
Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a ...
US-7,829,991 Stackable ceramic FBGA for high thermal applications
An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor...
US-7,829,979 High permeability layered films to reduce noise in high speed interconnects
An apparatus provides a memory having a transmission line circuit with an associated high permeability material. The high permeability material may include a...
US-7,829,976 Microelectronic devices and methods for forming interconnects in microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
US-7,829,938 High density NAND non-volatile memory device
Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that...
US-7,829,410 Methods of forming capacitors, and methods of forming DRAM arrays
Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric...
US-7,829,399 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,829,385 Taped semiconductor device and method of manufacture
Printed tape is used to form a leads on chip (LOC) ball grid array (BGA) semiconductor device. Leads for a plurality of devices may be applied simultaneously....
US-7,829,262 Method of forming pitch multipled contacts
Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching...
US-7,829,190 Electrical interconnect using locally conductive adhesive
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one...
US-7,827,226 Hybrid arithmetic logic unit
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a...
US-7,826,293 Devices and methods for a threshold voltage difference compensated sense amplifier
A voltage compensated sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to...
US-7,826,292 Precharge control circuits and methods for memory having buffered write commands
Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at...
US-7,826,290 Apparatus and method for increasing data line noise tolerance
Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage,...
US-7,826,274 Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
US-7,826,265 Memory device with variable trim setting
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one...
US-7,826,033 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,825,973 Exposure control for image sensors
An imaging system utilizes an exposure control circuit to control the length of an exposure in full frame mode. The exposure control circuit receives as an input...
US-7,825,711 Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals
Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive...
US-7,825,700 Integrated circuit comparator or amplifier
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
US-7,825,462 Transistors
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-7,825,452 Memory cell with buried digit line
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of...
US-7,825,451 Array of capacitors with electrically insulative rings
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,825,450 Sacrificial self-aligned interconnect structures
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material adjacent to an active region location and underlying...
US-7,825,443 Semiconductor constructions
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
US-7,825,414 Method of forming a thin film transistor
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
US-7,825,033 Methods of forming variable resistance memory cells, and methods of etching germanium, antimony, and...
A method of etching a material that includes comprising germanium, antimony, and tellurium encompasses exposing said material to a plasma-enhanced etching...
US-7,825,010 Die singulation methods
Some embodiments include methods in which a front side region of a semiconductor substrate is placed against a surface. While the front side region is against...
US-7,824,994 Method of forming memory devices by performing halogen ion implantation and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-7,824,986 Methods of forming a plurality of transistor gates, and methods of forming a plurality of transistor gates...
A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a...
US-7,824,983 Methods of providing electrical isolation in semiconductor structures
Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having...
US-7,824,982 DRAM arrays, vertical transistor structures, and methods of forming transistor structures and DRAM arrays
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The...
US-7,824,741 Method of forming a carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
US-7,824,505 Method to address carbon incorporation in an interpoly oxide
A method of removing a mask and addressing interfacial carbon chemisorbed in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip...
US-7,823,440 Systems and methods for characterizing thickness and topography of microelectronic workpiece layers
Metrology systems, tools, and methods that characterize one or more layers of a microelectronic workpiece are disclosed herein. In one embodiment, a system for...
US-7,823,024 Memory hub tester interface and method for use thereof
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a...
US-7,822,911 Memory device and method with on-board cache system for facilitating interface with multiple processors, and...
A memory device includes an on-board cache system that facilitates the ability of the memory device to interface with a plurality of processors operating in a...
US-7,822,904 Capturing read data
Various techniques for capturing read data from a memory bus are disclosed herein. In one embodiment, a computing system includes a memory device, a memory bus...
US-7,822,076 Apparatus for multiplexing signals through I/O pins
One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor...
US-7,821,848 External clock tracking pipelined latch scheme
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data...
US-7,821,831 Block erase for volatile memory
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a...
US-7,821,830 Flash memory device with redundant columns
Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns....
US-7,821,810 Phase change memory adaptive programming
Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed...
US-7,821,555 Multi path power for CMOS imagers
An analog signal chain for a CMOS active pixel sensor imaging system utilizes, for each amplification stage, a plurality of fixed gain amplifiers instead of a...
US-7,821,321 Semiconductor temperature sensor using bandgap generator circuit
A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators...
US-7,821,291 Digital calibration circuits, devices and systems including same, and methods of operation
A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a...
US-7,821,142 Intermediate semiconductor device structures
An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is...
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