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Patent # Description
US-7,754,576 Method of forming inside rough and outside smooth HSG electrodes and capacitor structure
A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a...
US-7,754,532 High density chip packages, methods of forming, and systems including same
Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into...
US-7,754,531 Method for packaging microelectronic devices
Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes...
US-7,754,522 Phase change memory structures and methods
Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce...
US-7,754,399 Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-7,754,395 Methods of forming and using reticles
Some embodiments include methods of treating reticles to provide backside masking across regions of the reticle to compensate for problems occurring during...
US-7,753,693 Contacts and electrical connecting apparatus using the same
An electrical connecting apparatus uses a plurality of contacts each of which includes: a principal portion having an outer face curved and directed to a...
US-RE41,441 Output buffer having inherently precise data masking
A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally...
US-7,752,381 Version based non-volatile memory translation layer
A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data...
US-7,751,634 Compression system for integrated sensor devices
An imaging system incorporating adaptive compression which includes determining linear predictive differential residuals from an imager array pixel row. The...
US-7,751,263 Data retention kill function
Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the...
US-7,751,260 Memory device having strobe terminals with multiple functions
A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device...
US-7,751,253 Analog sensing of memory cells with a source follower driver in a semiconductor memory device
Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One...
US-7,751,246 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful...
US-7,751,245 Programming sequence in NAND memory
An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source...
US-7,751,242 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
US-7,751,236 MEM suspended gate non-volatile memory
A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing...
US-7,751,228 Dielectric relaxation memory
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site...
US-7,750,449 Packaged semiconductor components having substantially rigid support members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
US-7,750,395 Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of...
US-7,750,389 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,750,379 Metal-substituted transistor gates
One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over...
US-7,750,344 Doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,749,899 Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
Methods and systems for forming electrical interconnects through microelectronic workpieces are disclosed herein. One aspect of the invention is directed to a...
US-7,749,887 Methods of fluxless micro-piercing of solder balls, and resulting devices
A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material,...
US-7,749,885 Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical...
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel...
US-7,749,882 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes...
US-7,749,879 ALD of silicon films on germanium
The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a...
US-7,749,860 Method for forming a self-aligned T-shaped isolation trench
The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical...
US-7,749,849 Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom
Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas...
US-7,749,848 Band-engineered multi-gated non-volatile memory device with enhanced attributes
Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate...
US-7,749,837 High coupling memory cell
A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric...
US-7,749,808 Stacked microelectronic devices and methods for manufacturing microelectronic devices
Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can...
US-7,749,786 Methods of forming imager systems
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,749,663 Method for adjusting dimensions of photomask features
A method for adjusting one or more dimensions of a photomask subsequent to etching of a defective pattern in the chrome-containing layer thereof is provided. The...
US-7,749,349 Methods and systems for releasably attaching support members to microfeature workpieces
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
US-7,749,327 Methods for treating surfaces
Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer...
US-7,747,933 Method and apparatus for detecting communication errors on a bus
A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on...
US-7,747,903 Error correction for memory
Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing...
US-7,747,890 Method and apparatus of high-speed input sampling
A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and...
US-7,747,090 Scan line to block re-ordering buffer for image compression
A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing...
US-7,746,959 Method and system for generating reference voltages for signal receivers
A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In...
US-7,746,720 Techniques for reducing leakage current in memory devices
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus...
US-7,746,710 Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
US-7,746,701 Semiconductor memory device having bit line pre-charge unit separated from data register
A semiconductor memory device is described that can, in certain embodiments, reduce a delay in access time and/or an area of a memory cell array. In one or more...
US-7,746,700 NAND architecture memory devices and operation
Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit...
US-7,746,691 Methods and apparatus utilizing predicted coupling effect in the programming of non-volatile memory
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized...
US-7,746,398 Wide dynamic range active pixel with knee response
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment a pixel circuit comprises a...
US-7,746,170 Class AB amplifier and imagers and systems using same
A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common...
US-7,745,944 Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated...
Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed...
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