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Patent # Description
US-7,767,365 Methods for forming and cleaning photolithography reticles
A method for removing impurities (e.g., atomic sulfur) from a reticle for use in photolithography is provided. In one embodiment, a reticle (or photomask)...
US-7,767,363 Methods for photo-processing photo-imageable material
The invention includes methods for photo-processing photo-imageable material. Locations of the photo-imageable material where flare hot spots are expected to...
US-7,767,129 Imprint templates for imprint lithography, and methods of patterning a plurality of substrates
The invention comprises methods of patterning a plurality of substrates, and imprint templates used in imprint lithography. In one implementation, a method of...
US-7,765,426 Emerging bad block detection
Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques...
US-7,765,424 System and method for injecting phase jitter into integrated circuit test signals
A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock...
US-7,764,567 Word line driver circuitry and methods for using the same
Word line driver circuitry for selectively, charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology,...
US-7,764,563 Adjustable voltage regulator for providing a regulated output voltage
Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator...
US-7,764,558 Hybrid sense amplifier and method, and memory device using same
Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit....
US-7,764,554 I/O circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state...
US-7,764,073 Electrical connecting apparatus
The electrical connecting apparatus comprises: a wiring base plate having a first surface provided with a plurality of first conductive portions; a probe base...
US-7,763,933 Transistor constructions and processing methods
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second...
US-7,763,548 Microfeature workpiece processing system for, e.g., semiconductor wafer analysis
The present disclosure suggests apparatus and methods that can be used to chemically process microfeature workpieces, e.g., semiconductor wafers. One...
US-7,763,499 CMOS front end process compatible low stress light shield
An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding...
US-7,763,497 Structure and method for forming a capacitively coupled chip-to-chip signaling interface
A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first...
US-7,763,453 Microfluidic mixing and analytic apparatus
Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles...
US-7,763,327 Methods using ozone for CVD deposited films
A CVD ozone (O.sub.3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and...
US-7,760,582 Apparatus for memory device wordline
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a...
US-7,760,533 Systems, methods and devices for arbitrating die stack position in a multi-bit stack device
Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked...
US-7,760,532 Multi-bank memory
A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another...
US-7,760,329 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
A method and structure for optimizing an optical lithography illumination source may include a shaped diffractive optical element (DOE) interposed between the...
US-7,760,019 Adaptive operational transconductance amplifier load compensation
A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The...
US-7,759,800 Microelectronics devices, having vias, and packaged microelectronic devices having vias
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and...
US-7,759,785 Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing...
Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing...
US-7,759,747 Tantalum aluminum oxynitride high-.kappa. dielectric
Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems...
US-7,759,724 Memory cells having gate structure with multiple gates and multiple materials between the gates
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell...
US-7,759,717 Capacitors comprising dielectric regions having first and second oxide material portions of the same chemical...
A capacitor includes a first capacitor electrode which includes conductive metal. A second capacitor electrode is spaced from the first capacitor electrode. A...
US-7,759,715 Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle
Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element...
US-7,759,665 PCRAM device with switching glass layer
A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.
US-7,759,660 Electron beam lithography system
Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary...
US-7,759,620 Fourier plane analysis and refinement of SLM calibration
The present disclosure relates to phase-sensitive calibration of an SLM system. In particular, it relates to selecting among local calibrations when there is...
US-7,759,240 Use of palladium in IC manufacturing with conductive polymer bump
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible...
US-7,759,237 Method of forming lutetium and lanthanum dielectric structures
Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide...
US-7,759,233 Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor...
Semiconductor material strips are secured to substrates in such a way as to stress the semiconductor material. The strips of semiconductor material may be...
US-7,759,221 Methods for packaging microelectronic devices and microelectronic devices formed using such methods
Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed...
US-7,759,197 Method of forming isolated features using pitch multiplication
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are...
US-7,759,193 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two...
US-7,759,187 Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
US-7,759,183 Dual work function metal gates and methods of forming
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a...
US-7,759,154 Ultrashallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,759,053 Methods of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a...
US-7,757,385 System for fabricating semiconductor components with through wire interconnects
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-7,757,061 System and method for decoding commands based on command signals and operating state
A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on...
US-7,755,940 Method, apparatus, and system for erasing memory
Methods, apparatus, and systems may operate such as to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. One...
US-7,755,939 System and devices including memory resistant to program disturb and methods of using, making, and operating...
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of...
US-7,755,684 Row driver circuitry for imaging devices and related method of operation
Row drivers as a part of an image sensor device include circuitry for supplying a plurality of signals with an increased voltage and enhanced reliability to a...
US-7,755,657 Method for high precision printing of patterns
The present invention includes a method to print patterns with improved edge acuity. The method for printing fine patterns comprises the actions of: providing an...
US-7,755,570 Microdisplay and interface on a single chip
A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same...
US-7,755,404 Delay locked loop circuit and method
Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a...
US-7,755,385 Method for operating an electronic device with reduced pin capacitance
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively...
US-7,755,316 Moving member movement control apparatus, moving member movement control method and machine tool movement...
A movement control apparatus for a moving member, includes: a drive unit that moves a moving member by rapid traverse on a first axis and a second axis...
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