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Patent # Description
US-7,729,189 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor...
US-7,729,182 Systems and methods for issuing address and data signals to a memory array
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked...
US-7,729,179 Random access memory employing read before write for resistance stabilization
An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase...
US-7,729,171 Multiple select gate architecture with select gates of different lengths
The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in...
US-7,729,167 Programming a memory with varying bits per cell
Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates...
US-7,729,163 Phase change memory
The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a...
US-7,728,896 Dual conversion gain gate and capacitor and HDR combination
A pixel circuit having a shared control line for providing two control signals to the pixel array. One control line is used to provide a control signal to both a...
US-7,728,639 Trimmable delay locked loop circuitry with improved initialization characteristics
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay...
US-7,728,626 Memory utilizing oxide nanolaminates
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a...
US-7,728,608 Method for assembling electrical connecting apparatus
A method for assembling an electrical connecting apparatus having a support member, a probe board, and spacers arranged between the support member and the probe...
US-7,728,574 Reference circuit with start-up control, generator, device, system and method including same
A reference generator circuit generates a reference signal for use by a regulator in generating operational power for circuits and devices. A start-up circuit...
US-7,728,443 Semiconductor components with through wire interconnects
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-7,728,350 Memory cell with negative differential resistance
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode...
US-7,727,910 Zirconium-doped zinc oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain...
US-7,727,908 Deposition of ZrA1ON films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
US-7,727,905 Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is arranged as a structure of one or more...
US-7,727,872 Methods for fabricating semiconductor components with conductive interconnects
A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching...
US-7,727,868 Apparatus and method for controlling diffusion
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,727,858 Method for fabricating a chip scale package using wafer level processing
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining...
US-7,727,840 Forming integrated circuit devices
Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask...
US-7,727,786 Photon-based memory device
An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material...
US-7,727,785 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach...
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL)...
US-7,724,592 Internal data comparison for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,724,577 NAND with back biased operation
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are...
US-7,724,564 Capacitive divider sensing of memory cells
The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable...
US-7,724,049 Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a...
Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises...
US-7,723,831 Semiconductor package having die with recess and discrete component embedded within the recess
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,723,767 High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
US-7,723,756 Silicon pillars for vertical transistors
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In...
US-7,723,713 Layered resistance variable memory device and method of fabrication
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,723,712 Reduced power consumption phase change memory and methods for forming the same
Memory cells for reduced power consumption and methods for forming the same are provided. A memory cell has a layer of phase change material. A first portion of...
US-7,723,227 Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry
A method of forming copper-comprising conductive lines in the fabrication of integrated circuitry includes depositing damascene material over a substrate. Line...
US-7,723,185 Flash memory with recessed floating gate
A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer...
US-7,723,166 Optoelectronic devices and solar cells
The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator...
US-7,723,009 Topography based patterning
A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a...
US-7,721,429 Method for manufacturing a probe
A probe formed on a base table is detached from the base table without giving damage on the probe. The present invention provides a probe manufacturing method...
US-7,721,175 System, apparatus, and method for memory built-in self testing using microcode sequencers
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into...
US-7,721,163 JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
US-7,720,654 Generation and manipulation of realistic signals for circuit and system verification
Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a...
US-7,720,341 Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
US-7,719,917 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-7,719,901 Solid state memory utilizing analog communication of data values
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-7,719,899 Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory
An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells....
US-7,719,888 Memory device having a negatively ramping dynamic pass voltage for reducing read-disturb effect
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to...
US-7,719,334 Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second...
US-7,719,300 Method for testing a semiconductor wafer and apparatus thereof
Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a...
US-7,719,120 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-7,719,065 Ruthenium layer for a dielectric layer containing a lanthanide oxide
A ruthenium layer for a dielectric layer containing a lanthanide layer and a method of fabricating such a combination of ruthenium layer and dielectric layer...
US-7,719,046 Apparatus and method for trench transistor memory having different gate dielectric thickness
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system...
US-7,719,044 Platinum-containing integrated circuits and capacitor constructions
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
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