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Patent # Description
US-7,804,171 Techniques for packaging a multiple device component
A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip...
US-7,804,168 Ball grid array structures having tape-based circuitry
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using...
US-7,804,144 Low-temperature grown high quality ultra-thin CoTiO.sub.3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,804,139 Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench
Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide....
US-7,804,115 Semiconductor constructions having antireflective portions
In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the...
US-7,803,686 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-7,802,157 Test mode for multi-chip integrated circuit packages
When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal...
US-7,800,965 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,800,953 Method and system for selectively limiting peak power consumption during programming or erase of non-volatile...
A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the...
US-7,800,947 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,800,815 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,800,657 Method, apparatus and system using hierarchical histogram for automatic exposure adjustment of an image
A method, apparatus and system with a hierarchical histogram generator that generates sub-histograms of differing resolutions. These sub-histograms are used to...
US-7,800,384 Probe unit substrate
A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the...
US-7,800,238 Surface depressions for die-to-die interconnects and associated systems and methods
Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of...
US-7,800,137 Semiconductor constructions
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a...
US-7,800,092 Phase change memory elements using energy conversion layers, memory arrays and systems including same, and...
A phase change memory element and method of forming the same. The memory element includes a phase change material layer electrically coupled to first and second...
US-7,800,042 Method and apparatus for setting black level in an imager using both optically black and tied pixels
An imaging pixel array includes an active area of pixels, organized into rows and columns of pixels. The array also includes a plurality of dark pixel columns...
US-7,800,001 Probe sheet and electrical connecting apparatus
An embodiment of a probe sheet enabling to restrict misalignment of the posture of each contactor accurately positioned on a probe sheet main body caused by...
US-7,799,694 Methods of forming semiconductor constructions
The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor...
US-7,799,610 Method of fabricating a stacked die having a recess in a die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided.
US-7,799,196 Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
US-7,799,180 Silver selenide sputtered films and method and apparatus for controlling defect formation in silver selenide...
Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A...
US-7,797,597 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating...
US-7,796,414 Memory module, system and method of making same
A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices...
US-7,795,934 Switched capacitor for a tunable delay circuit
A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a...
US-7,795,903 Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages....
US-7,795,737 Methods of redistributing bondpad locations on an integrated circuit
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
US-7,795,725 Semiconductor packages
The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon...
US-7,795,664 Finned memory cells
For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates...
US-7,795,152 Methods of making self-aligned nano-structures
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
US-7,795,149 Masking techniques and contact imprint reticles for dense semiconductor fabrication
A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars...
US-7,795,134 Conductive interconnect structures and formation methods using supercritical fluids
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
US-7,795,094 Recessed gate dielectric antifuse
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the...
US-7,795,093 Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-7,794,787 Methods of depositing materials over substrates, and methods of forming layers over substrates
The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is...
US-7,793,075 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,791,952 Memory device architectures and operation
Non-volatile memory devices logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks...
US-7,791,941 Non-volatile SRAM cell
Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring...
US-7,791,612 Fully associative texture cache having content addressable memory and method for use thereof
A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data...
US-7,791,388 Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction...
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal....
US-7,791,364 Electronic device probe card with improved probe grouping
The probe card includes a plurality of probes arranged on one surface side of a board. These probes belonging to any one of a first probe group including a...
US-7,791,207 Pass through via technology for use during the manufacture of a semiconductor device
Via structures are described which pass through a semiconductor substrate assembly such as a semiconductor die or wafer and allows for two different types of...
US-7,791,205 Interposers for semiconductor die packages with standard ball grill array footprint
Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to...
US-7,791,203 Interconnects for packaged semiconductor devices and methods for manufacturing such devices
Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a...
US-7,791,184 Image sensor packages and frame structure thereof
A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image...
US-7,791,143 Semiconductor constructions
In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anisotropically...
US-7,791,116 CMOS imager having a nitride dielectric
An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen...
US-7,791,071 Profiling solid state samples
Methods and apparatus may operate to position a sample, including an imager lens surface, within a processing chamber. Further activities may include creating a...
US-7,791,058 Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and...
A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable...
US-7,791,055 Electron induced chemical etching/deposition for enhanced detection of surface defects
A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than...
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