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Patent # Description
US-7,746,700 NAND architecture memory devices and operation
Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit...
US-7,746,691 Methods and apparatus utilizing predicted coupling effect in the programming of non-volatile memory
Methods and memory devices configured to utilize predicted coupling effects of neighboring memory cells in the programming of target memory cells can be utilized...
US-7,746,398 Wide dynamic range active pixel with knee response
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment a pixel circuit comprises a...
US-7,746,170 Class AB amplifier and imagers and systems using same
A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common...
US-7,745,944 Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated...
Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed...
US-7,745,942 Die package and probe card structures and fabrication methods
A semiconductor die has conductors encapsulated in a dielectric material disposed on the active surface extending across the active surface from bond pads to one...
US-7,745,934 Integrated circuit and seed layers
Structures are provided that include a conducting layer disposed on a layered arrangement of a diffusion barrier layer and a seed layer in an integrated circuit....
US-7,745,920 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-7,745,900 Method and apparatus providing refractive index structure for a device capturing or displaying images
A transient index stack having an intermediate transient index layer, for use in an imaging device or a display device, that reduces reflection between layers...
US-7,745,873 Ultra-thin body vertical tunneling transistor
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on...
US-7,745,808 Differential negative resistance memory
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes...
US-7,745,319 System and method for fabricating a fin field effect transistor
There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising...
US-7,745,295 Methods of forming memory cells
Some embodiments include methods of forming memory cells. Dopant is implanted into a semiconductor substrate to form a pair of source/drain regions that are...
US-7,745,283 Method of fabricating memory transistor
A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At...
US-7,745,231 Resistive memory cell fabrication methods and devices
A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom...
US-7,743,303 Defective memory block remapping method and system, and memory device and processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output...
US-7,742,344 Method and apparatus for improving storage performance using a background erase
Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of...
US-7,742,338 Local self-boost inhibit scheme with shielded word line
A NAND architecture non-volatile memory device and programming process is described that reduces the effects of word line to word line voltage coupling by...
US-7,742,335 Non-volatile multilevel memory cells
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes...
US-7,742,324 Systems and devices including local data lines and methods of using, making, and operating the same
Disclosed are methods, systems and devices, including a device having a fin field-effect transistor with a first terminal, a second terminal, and two gates. In...
US-7,742,313 Stacked microfeature devices
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-7,741,873 Receiver circuitry for receiving reduced swing signals from a channel
A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power...
US-7,741,660 Pixel and imager device having high-k dielectrics in isolation structures
An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention...
US-7,741,589 Method and apparatus providing multiple transfer gate control lines per pixel for automatic exposure control
An imager device includes a pixel array having some pixels providing output signals for automatic light control with other pixels providing image output signals....
US-7,741,175 Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
US-7,741,150 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing...
US-7,739,576 Variable strength ECC
Memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory controllers, memory systems, and/or...
US-7,738,988 Process and method for continuous, non lot-based integrated circuit manufacturing
A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes:...
US-7,738,310 Fuse data acquisition
One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment...
US-7,738,295 Programming a non-volatile memory device
A non-volatile memory device that has a cache register coupled between each pair of bit lines and, in one embodiment, a data cache coupled between each pair of...
US-7,738,294 Programming multilevel cell memory arrays
Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one...
US-7,738,292 Flash memory with multi-bit read
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory...
US-7,738,291 Memory page boosting method, device and system
A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes...
US-7,737,741 Periodic signal delay apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to...
US-7,737,729 Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
US-7,737,559 Semiconductor constructions
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-7,737,536 Capacitive techniques to reduce noise in high speed interconnections
Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits....
US-7,737,394 Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
US-7,737,055 Systems and methods for manipulating liquid films on semiconductor substrates
A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a...
US-7,737,047 Semiconductor constructions, and methods of forming dielectric materials
Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two...
US-7,737,039 Spacer process for on pitch contacts and related structures
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated...
US-7,737,024 Small grain size, conformal aluminum interconnects and method for their formation
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
US-7,737,022 Contact formation
The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator...
US-7,737,010 Method of photoresist strip for plasma doping process of semiconductor manufacturing
A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the...
US-7,736,987 Methods of forming semiconductor constructions
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,736,980 Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
US-7,736,969 DRAM layout with vertical FETS and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,736,690 Method for manufacturing an electrical test probe
A probe tip section of an electrical test probe has a laminated structure consisting of a first deposition portion and a second deposition portion covering the...
US-7,735,221 Method for manufacturing a multilayer wiring board
A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is...
US-7,734,899 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
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