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Patent # Description
US-7,781,877 Packaged integrated circuit devices with through-body conductive vias, and methods of making same
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at...
US-7,781,875 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-7,781,868 Semiconductor components having through interconnects and backside redistribution conductors
A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality...
US-7,781,860 Semiconductor constructions, and electronic systems
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can...
US-7,781,818 Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions...
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,779,212 Method and apparatus for sending data from multiple sources over a communications bus
In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives...
US-7,778,812 Selecting data to verify in hardware device model simulation test generation
Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate...
US-7,778,092 Memory system and method having volatile and non-volatile memory devices at same hierarchical level
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer...
US-7,778,086 Erase operation control sequencing apparatus, systems, and methods
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate....
US-7,778,039 Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods...
Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress...
US-7,777,287 System and apparatus providing analytical device based on solid state image sensor
An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of analytical...
US-7,777,264 Random access memory device utilizing a vertically oriented select transistor
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor...
US-7,776,765 Tantalum silicon oxynitride high-k dielectrics and metal gates
Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic...
US-7,776,762 Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of...
US-7,776,749 Methods of forming semiconductor constructions
The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth...
US-7,776,744 Pitch multiplication spacers and methods of forming the same
Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the...
US-7,776,715 Reverse construction memory cell
A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a...
US-7,776,683 Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a...
US-7,776,652 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,776,647 Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside...
A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts...
US-7,775,710 DRAM temperature management system
A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a...
US-7,774,683 Erasure pointer error correction
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in...
US-7,774,559 Method and system for terminating write commands in a hub-based memory system
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write...
US-7,774,536 Power up initialization for memory
A memory device is described that enhances initialization of the memory device. In the prior art, initialization of synchronous Flash memory requires the release...
US-7,773,492 Method and apparatus providing high density data storage
A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data...
US-7,773,441 Memory malfunction prediction system and method
A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of...
US-7,773,418 Non-volatile memory with both single and multiple level cells
Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed...
US-7,773,412 Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted,...
US-7,772,908 Voltage and temperature compensation delay system and method
A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input...
US-7,772,680 Arrangements of fuse-type constructions
The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of...
US-7,772,672 Semiconductor constructions
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
US-7,772,635 Non-volatile memory device with tensile strained silicon layer
A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that...
US-7,772,633 DRAM cells with vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-7,772,632 Memory arrays and methods of fabricating memory arrays
A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect...
US-7,772,583 Memory devices and methods of forming the same
Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The...
US-7,772,537 Linear distributed pixel differential amplifier having mirrored inputs
A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the...
US-7,772,116 Methods of forming blind wafer interconnects
Methods for forming blind wafer interconnects (BWIs) from the back side of a previously thinned substrate structure such as a semiconductor wafer to the...
US-7,772,115 Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems...
A method for forming through-wafer interconnects (TWI) in a substrate of a thickness in excess of that of a semiconductor die such as a semiconductor wafer....
US-7,772,066 DRAM tunneling access transistor
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side...
US-7,771,917 Methods of making templates for use in imprint lithography
A method of forming a template for use in imprint lithography. The method comprises providing an ultraviolet ("UV") wavelength radiation transparent layer and...
US-7,771,537 Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition
The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in...
US-7,771,220 Electrical connecting apparatus
An embodiment of an electrical connecting apparatus comprises an electrical insulating plate, an elastic plate made of an electrical insulating material arranged...
US-7,771,115 Temperature sensor circuit, device, system, and method
A sensor, device, system and method for sensing temperature includes a pull up circuit coupled to a pull down circuit for generating a variable pull up output...
US-7,770,079 Error scanning in flash memory
Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is...
US-7,769,286 Method and apparatus of determining the best focus position of a lens
A method and apparatus for accurately auto focusing a lens of an imaging device. An imaged scene is split into an array of zones. The minimum and maximum...
US-7,768,868 Digital filters for semiconductor devices
A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the...
US-7,768,861 Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
US-7,768,846 Individual I/O modulation in memory devices
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are...
US-7,768,839 Memory read methods, apparatus, and systems
Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to...
US-7,768,838 Operating memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a...
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