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Patent # Description
US-7,705,429 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,705,389 Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a...
US-7,705,383 Integrated circuitry for semiconductor memory
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor...
US-7,705,349 Test inserts and interconnects with electrostatic discharge structures
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD...
US-7,704,884 Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
US-7,704,849 Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-7,704,794 Method of forming a semiconductor device
A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than...
US-7,704,673 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-7,702,949 Use of non-volatile memory to perform rollback function
A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is...
US-7,701,788 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,701,782 Signal transfer apparatus and methods
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of...
US-7,701,780 Non-volatile memory cell healing
Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first...
US-7,701,776 Low power multiple bit sense amplifier
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers...
US-7,701,765 Non-volatile multilevel memory cell programming
The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower...
US-7,701,764 Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory...
US-7,701,763 Leakage compensation during program and read operations
Methods of operating a memory and a memory are disclosed, such as an analog non-volatile memory device and process that reduces the effects of charge leakage...
US-7,701,762 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
US-7,701,760 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,701,741 Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell...
US-7,701,493 Imager row-wise noise correction
An imager having optically and electrically black reference pixels in each row of the imager's pixel array. Since the reference pixels of each row experience the...
US-7,701,462 Simple and robust color saturation adjustment for digital images
A method and system for adjusting saturation in digital images that operates as closely as possible to the long-, medium-, short-(LMS) cone spectral response...
US-7,701,443 Ergonomic computer mouse
An ergonomic computer mouse is provided. The mouse has at least one signaling device that is positioned to accommodate a user's fingers when they are in a...
US-7,701,272 Method and apparatus for output data synchronization with system clock
A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to...
US-7,701,184 Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate...
US-7,701,059 Low resistance metal silicide local interconnects and a method of making
A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of...
US-7,701,039 Semiconductor devices and in-process semiconductor devices having conductor filled vias
At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element...
US-7,700,989 Hafnium titanium oxide films
Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an...
US-7,700,497 Methods for fabricating residue-free contact openings
A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures...
US-7,700,485 Electro- and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
US-7,700,480 Methods of titanium deposition
Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to...
US-7,700,478 Intermediate anneal for metal deposition
The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process...
US-7,700,469 Methods of forming semiconductor constructions
Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second...
US-7,700,441 Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of...
The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry...
US-7,700,436 Method for forming a microelectronic structure having a conductive material and a fill material with a hardness...
A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the...
US-7,700,422 Methods of forming memory arrays for increased bit density
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
US-7,700,406 Methods of assembling integrated circuit packages
Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of...
US-7,699,998 Method of substantially uniformly etching non-homogeneous substrates
A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including...
US-7,699,932 Reactors, systems and methods for depositing thin films onto microfeature workpieces
A reactor, system including reactors, and methods for depositing thin films on microfeature workpieces comprising a reaction vessel having a chamber, a gas...
US-7,699,630 Memory module having a cover pivotally coupled thereto
A storage device has a memory module and a cover pivotally coupled to a housing of the memory module. In one such storage device, the memory module and cover can...
US-7,698,499 Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change...
US-7,697,357 Negative voltage driving for the digit line isolation gates
A system and method to reduce standby leakage current in the event of row-to-column shorts in a memory chip or in an electronic device having memory or data...
US-7,697,335 Multiple select gate architecture
Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing...
US-7,697,328 Split gate flash memory cell with ballistic injection
A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of...
US-7,697,324 Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
US-7,696,778 Systems and methods for detecting terminal state and setting output driver impedance
Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to...
US-7,696,624 Nucleation method for atomic layer deposition of cobalt on bare silicon during the formation of a semiconductor...
A method used to form a cobalt metal layer on a silicon surface using an atomic layer deposition (ALD) process comprises a treatment of the silicon surface prior...
US-7,696,579 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,696,568 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-7,696,567 Semiconductor memory device
A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical...
US-7,696,557 Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and...
Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column...
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