Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: micron
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,951,414 |
Methods of forming electrically conductive structures Some embodiments include methods of forming conductive material within high aspect ratio openings and low aspect ratio openings. Initially, the high aspect... |
| US-7,949,844 |
Pipelined burst memory access A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to... |
| US-7,949,822 |
Storage capacity status In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated... |
| US-7,949,821 |
Method of storing data on a flash memory device Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block... |
| US-7,949,803 |
System and method for transmitting data packets in a computer system
having a memory hub architecture A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled... |
| US-7,948,821 |
Reduced signal interface memory device, system, and method A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad.... |
| US-7,948,802 |
Sensing memory cells The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to... |
| US-7,948,793 |
Temperature compensation in memory devices and systems Devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory are included. A... |
| US-7,948,786 |
Rank select using a global select pin Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system,... |
| US-7,948,279 |
Clock divider There is provided a true single phase logic clock divider that is configured to selectively divide a clock signal by increments of two, three, four, or six.... |
| US-7,948,030 |
Semiconductor constructions of memory devices with different sizes of
GateLine trenches Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.3. The recessed... |
| US-7,948,008 |
Floating body field-effect transistors, and methods of forming floating
body field-effect transistors In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween.... |
| US-7,947,601 |
Semiconductor devices and methods for forming patterned radiation blocking
on a semiconductor device Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for... |
| US-7,947,597 |
Methods of titanium deposition Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to... |
| US-7,947,543 |
Recessed gate silicon-on-insulator floating body device with self-aligned
lateral isolation Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This... |
| US-7,947,529 |
Microelectronic die packages with leadframes, including leadframe-based
interposer for stacked die packages,... Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of... |
| US-7,947,412 |
Reduced lens heating methods, apparatus, and systems In one embodiment, a system is disclosed that includes an illuminator having a source that produces light waves having a first wavelength, and a mask. The mask... |
| US-7,946,855 |
Contact and electrical connecting apparatus A contact type electrical connector includes a first plunger in contact with one member; a second plunger in contact with another member and electrically... |
| US-7,945,840 |
Memory array error correction apparatus, systems, and methods Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being... |
| US-7,944,773 |
Synchronous command-based write recovery time auto-precharge control Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous... |
| US-7,944,768 |
Software refreshed memory device and method A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells... |
| US-7,944,764 |
Writing to non-volatile memory during a volatile memory refresh cycle Writing to non-volatile memory during a volatile memory refresh cycle is described. In one example, a write command is received and data is received to write... |
| US-7,944,762 |
Non-volatile memory control Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a... |
| US-7,944,761 |
Memory device having strobe terminals with multiple functions A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device... |
| US-7,944,757 |
Non-volatile multilevel memory cell programming Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method... |
| US-7,944,755 |
Erase verify in memory devices In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a... |
| US-7,944,748 |
Erase block data splitting A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data... |
| US-7,944,743 |
Methods of making a semiconductor memory device One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base... |
| US-7,944,738 |
Spin torque transfer cell structure utilizing field-induced
antiferromagnetic or ferromagnetic coupling A magnetic memory cell including a soft magnetic layer and a coupling layer, and methods of operating the memory cell are provided. The memory cell includes a... |
| US-7,944,485 |
Method, apparatus and system for dynamic range estimation of imaged scenes A method, apparatus, and system for dynamic range estimation of imaged scenes for automatic exposure control. For a given exposure time setting, certain areas... |
| US-7,944,300 |
Bias circuit and amplifier providing constant output current for a range
of common mode inputs Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a... |
| US-7,944,234 |
Programmable on-chip logic analyzer apparatus, systems, and methods Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to... |
| US-7,944,025 |
Semiconductor constructions The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a... |
| US-7,944,019 |
Voltage-controlled semiconductor inductor and method A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor... |
| US-7,943,921 |
Phase change current density control structure A phase change memory element and method of forming the same. The memory element includes first and second electrodes. A first layer of phase change material is... |
| US-7,943,505 |
Advanced VLSI metallization A four layer interconnect structure is disclosed which includes a bottom conductive reactive layer such as titanium, a conductive barrier layer, such as... |
| US-7,943,503 |
Trench interconnect structure and formation method Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in... |
| US-7,943,501 |
Systems and methods of forming tantalum silicide layers A method of forming (and apparatus for forming) tantalum silicide layers (including tantalum silicon nitride layers), which are typically useful as diffusion... |
| US-7,943,463 |
Methods of semiconductor processing involving forming doped polysilicon on
undoped polysilicon A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular... |
| US-7,943,422 |
Wafer level pre-packaged flip chip Methods for producing a flip chip package by prepackaging one or more dice on a semiconductor wafer are provided. An embodiment of the method includes applying... |
| US-7,941,712 |
Method for error test, recordation and repair In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test.... |
| US-7,941,056 |
Optical interconnect in high-speed memory systems A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of... |
| US-7,940,569 |
Power off apparatus, systems, and methods Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as... |
| US-7,940,568 |
Dynamic polarization for reducing stress induced leakage current Subject matter disclosed herein relates to non-volatile flash memory, and more particularly to a method of reducing stress induced leakage current. |
| US-7,940,559 |
Memory array having a programmable word length, and method of operating
same A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or... |
| US-7,940,556 |
Resistance variable memory device with sputtered metal-chalcogenide region
and method of fabrication A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of... |
| US-7,940,103 |
Duty cycle correction systems and methods Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a... |
| US-7,940,078 |
Method and apparatus for output driver calibration, and memory devices and
system embodying same A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration... |
| US-7,939,949 |
Semiconductor device with copper wirebond sites and methods of making same Semiconductor devices with external wirebond sites that include copper and methods for fabricating such semiconductor devices are disclosed. One embodiment of a... |
| US-7,939,948 |
Interconnect structures with bond-pads and methods of forming bump sites
on bond-pads Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.