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Patent # Description
US-7,723,166 Optoelectronic devices and solar cells
The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator...
US-7,723,009 Topography based patterning
A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a...
US-7,721,429 Method for manufacturing a probe
A probe formed on a base table is detached from the base table without giving damage on the probe. The present invention provides a probe manufacturing method...
US-7,721,175 System, apparatus, and method for memory built-in self testing using microcode sequencers
Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions into...
US-7,721,163 JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
US-7,720,654 Generation and manipulation of realistic signals for circuit and system verification
Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a...
US-7,720,341 Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
US-7,719,917 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-7,719,901 Solid state memory utilizing analog communication of data values
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-7,719,899 Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory
An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells....
US-7,719,888 Memory device having a negatively ramping dynamic pass voltage for reducing read-disturb effect
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to...
US-7,719,334 Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second...
US-7,719,300 Method for testing a semiconductor wafer and apparatus thereof
Reliability of results of a test such as a wafer burn-in test is raised. The present invention is a method for testing a plurality of semiconductor devices in a...
US-7,719,120 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-7,719,065 Ruthenium layer for a dielectric layer containing a lanthanide oxide
A ruthenium layer for a dielectric layer containing a lanthanide layer and a method of fabricating such a combination of ruthenium layer and dielectric layer...
US-7,719,046 Apparatus and method for trench transistor memory having different gate dielectric thickness
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system...
US-7,719,044 Platinum-containing integrated circuits and capacitor constructions
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
US-7,718,533 Inverted variable resistance memory cell and method of making the same
An inverted variable resistance memory cell and a method of fabricating the same. The memory cell is fabricated by forming an opening in an insulating layer...
US-7,718,495 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field...
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one...
US-7,718,084 Etchants for selectively removing dielectric materials
A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a dielectric layer overlying another dielectric...
US-7,718,080 Electronic beam processing device and method using carbon nanotube emitter
Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching...
US-RE41,340 Pinned photodiode photodetector with common buffer transistor and binning capability
.[.A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is...
US-7,716,510 Timing synchronization circuit with loop counter
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter....
US-7,715,641 Graphics engine for high precision lithography
The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability...
US-7,715,239 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,715,234 Reducing effects of program disturb in a memory device
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the...
US-7,714,617 Signal driver circuit having an adjustable output voltage
Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a...
US-7,714,322 Nanoparticle positioning technique
Embodiments of the present invention are generally directed to a method for disposing nanoparticles on a substrate. In one embodiment, a substrate having a...
US-7,713,885 Methods of etching oxide, reducing roughness, and forming capacitor constructions
The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1.times.10.sup.-6...
US-7,713,857 Methods of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry
A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through...
US-7,713,841 Methods for thinning semiconductor substrates that employ support structures formed on the substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor...
US-7,713,817 Methods of forming semiconductor structures
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be...
US-7,713,813 Methods of forming capacitors
The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a...
US-7,713,430 Using positive DC offset of bias RF to neutralize charge build-up of etch features
Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma...
US-7,712,211 Method for packaging circuits and packaged circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate...
US-7,710,805 Maintenance of amplified signals using high-voltage-threshold transistors
Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate...
US-7,710,786 NAND flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a...
US-7,710,765 Back gated SRAM cell
Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes...
US-7,710,760 Method and apparatus for charging large capacitances
A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator...
US-7,710,634 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,709,946 Micro universal serial bus (USB) memory package
A micro USB memory package and method for manufacturing the same, which can meet the USB standard specification, can have a light, thin, short and small...
US-7,709,885 Access transistor for memory device
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second...
US-7,709,877 High surface area capacitor structures and precursors
A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low...
US-7,709,777 Pumps for CMOS imagers
A pixel for an imaging device is described. The pixel includes a photosensitive device provided within a substrate for providing photo-generated charges, a...
US-7,709,402 Conductive layers for hafnium silicon oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON...
US-7,709,399 Atomic layer deposition systems and methods including metal .beta.-diketiminate compounds
The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one .beta.-diketiminate ligand. Such...
US-7,709,390 Methods of isolating array features during pitch doubling processes and semiconductor device structures having...
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one...
US-7,709,345 Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth...
US-7,709,343 Use of a plasma source to form a layer during the formation of a semiconductor device
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
US-7,709,341 Methods of shaping vertical single crystal silicon walls and resulting structures
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon...
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