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Patent # Description
US-7,736,980 Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
US-7,736,969 DRAM layout with vertical FETS and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,736,690 Method for manufacturing an electrical test probe
A probe tip section of an electrical test probe has a laminated structure consisting of a first deposition portion and a second deposition portion covering the...
US-7,735,221 Method for manufacturing a multilayer wiring board
A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is...
US-7,734,899 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-7,734,891 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-7,733,731 Control of inputs to a memory device
A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the...
US-7,733,705 Reduction of punch-through disturb during programming of a memory device
A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing...
US-7,733,699 Mimicking program verify drain resistance in a memory device
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the...
US-7,733,557 Spatial light modulators with changeable phase masks for use in holographic data storage
A holographic data storage system that includes a write head that includes a pixellated spatial light modulator and a separate or integral phase mask that varies...
US-7,733,392 Method and apparatus for reducing effects of dark current and defective pixels in an imaging device
A method and apparatus for identifying and compensating for the effects of defective pixels in high resolution digital cameras having image processing apparatus....
US-7,733,262 Quantizing circuits with variable reference signals
Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a...
US-7,733,118 Devices and methods for driving a signal off an integrated circuit
Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an...
US-7,732,882 Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
US-7,732,852 High-K dielectric materials and processes for manufacturing them
High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition...
US-7,732,533 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
US-7,732,343 Simplified pitch doubling process flow
A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further...
US-7,732,247 Isolation techniques for reducing dark current in CMOS image sensors
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an...
US-7,732,221 Hybrid MRAM array structure and operation
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ...
US-7,730,372 Device and method for testing integrated circuit dice in an integrated circuit module
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse...
US-7,729,197 Memory device having a delay locked loop with frequency control
Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the...
US-7,729,191 Memory device command decoding system and memory device and processor-based system using same
Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to...
US-7,729,189 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor...
US-7,729,182 Systems and methods for issuing address and data signals to a memory array
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked...
US-7,729,179 Random access memory employing read before write for resistance stabilization
An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase...
US-7,729,171 Multiple select gate architecture with select gates of different lengths
The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in...
US-7,729,167 Programming a memory with varying bits per cell
Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates...
US-7,729,163 Phase change memory
The present disclosure includes devices and methods for operating phase change memory cells. One or more embodiments include applying a programming signal to a...
US-7,728,896 Dual conversion gain gate and capacitor and HDR combination
A pixel circuit having a shared control line for providing two control signals to the pixel array. One control line is used to provide a control signal to both a...
US-7,728,639 Trimmable delay locked loop circuitry with improved initialization characteristics
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay...
US-7,728,626 Memory utilizing oxide nanolaminates
Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a...
US-7,728,608 Method for assembling electrical connecting apparatus
A method for assembling an electrical connecting apparatus having a support member, a probe board, and spacers arranged between the support member and the probe...
US-7,728,574 Reference circuit with start-up control, generator, device, system and method including same
A reference generator circuit generates a reference signal for use by a regulator in generating operational power for circuits and devices. A start-up circuit...
US-7,728,443 Semiconductor components with through wire interconnects
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-7,728,350 Memory cell with negative differential resistance
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode...
US-7,727,910 Zirconium-doped zinc oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain...
US-7,727,908 Deposition of ZrA1ON films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
US-7,727,905 Zirconium-doped tantalum oxide films
Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is arranged as a structure of one or more...
US-7,727,872 Methods for fabricating semiconductor components with conductive interconnects
A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching...
US-7,727,868 Apparatus and method for controlling diffusion
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,727,858 Method for fabricating a chip scale package using wafer level processing
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining...
US-7,727,840 Forming integrated circuit devices
Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask...
US-7,727,786 Photon-based memory device
An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material...
US-7,727,785 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach...
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL)...
US-7,724,592 Internal data comparison for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,724,577 NAND with back biased operation
Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are...
US-7,724,564 Capacitive divider sensing of memory cells
The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable...
US-7,724,049 Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a...
Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises...
US-7,723,831 Semiconductor package having die with recess and discrete component embedded within the recess
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,723,767 High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
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