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Patent # Description
US-7,687,836 Capacitance noise shielding plane for imager sensor devices
A conductive shield plane electrically isolating the photodiode regions from metal interconnect lines in an imager sensor device.
US-7,687,796 Method and apparatus for forming an integrated circuit electrode having a reduced contact area
A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a...
US-7,687,793 Resistance variable memory cells
An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material...
US-7,687,409 Atomic layer deposited titanium silicon oxide films
A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a...
US-7,687,408 Method for integrated circuit fabrication using pitch multiplication
Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed...
US-7,687,406 Methods of eliminating pattern collapse on photoresist patterns
A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The...
US-7,687,402 Methods of making optoelectronic devices, and methods of making solar cells
The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator...
US-7,687,358 Methods of forming a gated device
This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device...
US-7,687,342 Method of manufacturing a memory device
A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are...
US-7,687,329 Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this...
US-7,686,874 Electroless plating bath composition and method of use
An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An...
US-7,686,238 Powder processing method
In order to manufacture the compound powder or the porous granulated substance in an efficient manner, a powder processing apparatus has an accumulating face on...
US-7,684,276 Techniques for configuring memory systems using accurate operating parameters
Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically,...
US-7,684,266 Serial system for blowing antifuses
A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from...
US-7,684,243 Reducing read failure in a memory device
Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is...
US-7,684,237 Reading non-volatile multilevel memory cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes...
US-7,684,235 Phase change memory
A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing...
US-7,684,228 Device and method for using dynamic cell plate sensing in a DRAM memory cell
A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass...
US-7,684,227 Resistive memory architectures with multiple memory cells per access device
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is...
US-7,683,671 Method, apparatus, and system providing power supply independent imager output driver having a constant slew rate
An output driver having an output that is not dependant on the variation of the voltage level of a variable supply voltage. The output driver, having at least...
US-7,683,481 Bottom electrode for memory device and method of forming the same
Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a...
US-7,683,458 Through-wafer interconnects for photoimager and memory wafers
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making...
US-7,683,456 Semiconductor devices, capacitor antifuses, dynamic random access memories, and cell plate bias connection methods
In one aspect, a semiconductor device includes an array of memory cells. Individual memory cells of the array include a capacitor having first and second...
US-7,683,424 Ballistic direct injection NROM cell on strained silicon structures
A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the...
US-7,683,413 Double sided container capacitor for a semiconductor device
A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a...
US-7,683,306 Dual conversion gain gate and capacitor combination
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective...
US-7,683,022 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,683,021 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,683,020 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,683,001 Dielectric layers and memory cells including metal-doped alumina
A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,682,992 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,682,977 Methods of forming trench isolation and methods of forming arrays of FLASH memory cells
This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is...
US-7,682,962 Method for fabricating stacked semiconductor components with through wire interconnects
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-7,682,924 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises...
US-7,682,869 Method of packaging integrated circuit devices using preformed carrier
Disclosed is a method of packaging integrated circuit devices using a preformed carrier. In one illustrative embodiment, the method includes providing a carrier...
US-7,682,847 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,681,163 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric...
US-7,681,006 Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
US-7,681,005 Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
US-7,679,961 Programming and/or erasing a memory device in response to its program and/or erase history
For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a number...
US-7,679,389 Probe for electrical test and electrical connecting apparatus using it
A probe includes an arm region extending in the back and forth direction, and a tip region extending downward from the front end portion of the arm region. The...
US-7,679,198 Circuit and method for interconnecting stacked integrated circuit dies
Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective...
US-7,679,193 Use of AIN as cooper passivation layer and thermal conductor
A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer...
US-7,679,179 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,679,118 Vertical transistor, memory cell, device, system and method of forming same
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally...
US-7,678,708 Systems and methods for forming metal oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-7,678,691 Method of making a semiconductor device having improved contacts
A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In...
US-7,678,678 Method to chemically remove metal impurities from polycide gate sidewalls
An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a...
US-7,678,648 Subresolution silicon features and methods for forming the same
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and...
US-7,678,460 Intermediate semiconductor device structures using photopatternable, dielectric materials
A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously...
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