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Patent # Description
US-7,675,324 Pre-driver logic
At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives...
US-7,675,169 Apparatus and method for packaging circuits
Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The...
US-7,675,131 Flip-chip image sensor packages and methods of fabricating the same
There is provided an imager package including an image sensor die attached to a transparent substrate such that sensitive image sensing components on the sensor...
US-7,675,093 Antiblooming imaging apparatus, system, and methods
Apparatus, systems and methods are described to assist in reducing dark current in an active pixel sensor. A potential barrier arrangement is configured to block...
US-7,674,698 Metal-substituted transistor gates
One aspect of this disclosure relates to a method for forming an integrated circuit. According to various embodiments of the method, a plurality of transistors...
US-7,674,683 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a...
US-7,674,670 Methods of forming threshold voltage implant regions
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger...
US-7,674,669 FIN field effect transistor
Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium...
US-7,674,655 Semiconductor assemblies and methods of manufacturing such assemblies including forming trenches in a first...
Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of...
US-7,674,652 Methods of forming an integrated circuit package
A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top...
US-7,673,094 Memory devices with buffered command address bus
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased...
US-7,672,171 Non-planar flash memory array with shielded floating gates on silicon mesas
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of...
US-7,671,914 Increasing readout speed in CMOS APS sensors through block readout
A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the...
US-7,671,648 System and method for an accuracy-enhanced DLL during a measure initialization mode
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay...
US-7,671,647 Apparatus and method for trimming static delay of a synchronizing circuit
A system and method for trimming an unadjusted forward delay of a delay-locked loop (DLL) and trimming a duty cycle of first and second output clock signals...
US-7,671,644 Process insensitive delay line
A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The...
US-7,671,459 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can...
US-7,671,407 Embedded trap direct tunnel non-volatile memory
The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over...
US-7,670,958 Etching methods
An etching method includes applying a photoresist over a substrate, forming an opening in the photoresist, and etching the substrate under the opening using a...
US-7,670,907 Isolation regions for semiconductor devices and their formation
A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas...
US-7,670,905 Semiconductor processing methods, and methods of forming flash memory structures
Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the bottom...
US-7,670,898 Methods of forming semiconductor constructions
The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor...
US-7,670,646 Methods for atomic-layer deposition
Atomic-Layer deposition systems and methods provide a variety of electronic products. In an embodiment, a method uses an atomic-layer deposition system that...
US-7,670,469 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical...
US-7,670,466 Methods and apparatuses for electrochemical-mechanical polishing
Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a...
US-D611,035 Speaker
US-7,669,092 Apparatus, method, and system of NAND defect management
Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block...
US-7,669,064 Diagnostic and managing distributed processor system
A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a...
US-7,669,027 Memory command delay balancing in a daisy-chained memory topology
A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the...
US-7,668,893 Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders
Some embodiments of the invention includes a data generator. The data generator includes a data generating circuit having a combination of linear feedback shift...
US-7,668,012 Memory cell programming
One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states....
US-7,668,000 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive...
US-7,667,632 Quantizing circuits for semiconductor devices
An electronic device that includes an internal data storage location coupled to an electrical conductor and a quantizing circuit coupled to the internal data...
US-7,667,472 Probe assembly, method of producing it and electrical connecting apparatus
A probe assembly for use in electrical measurement of a device under test. The probe assembly comprises a plate-like probe base plate with bending deformation...
US-7,667,260 Nanoscale floating gate and methods of formation
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first...
US-7,667,258 Double-sided container capacitors using a sacrificial layer
Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is...
US-7,667,234 High density memory array having increased channel widths
A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that...
US-7,666,801 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,666,797 Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative...
The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for...
US-7,666,788 Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
US-7,666,776 Methods of forming conductive structures
The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material...
US-7,666,578 Efficient pitch multiplication process
Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated...
US-7,664,999 Real time testing using on die termination (ODT) circuit
A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is...
US-7,664,216 Digital frequency locked delay line
A device includes a signal generator having a delay locked circuit for providing a of output signals based on an input signal. The output signals have a fixed...
US-7,663,952 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of...
US-7,663,934 Program method with optimized voltage level for flash memory
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the...
US-7,663,930 Programming a non-volatile memory device
A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial...
US-7,663,926 Cell deterioration warning apparatus and method
Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate...
US-7,663,925 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-7,663,901 Techniques for implementing accurate device parameters stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique device parameters corresponding to specific memory devices on the...
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