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Patent # Description
US-7,663,137 Phase change memory cell and method of formation
A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase...
US-7,663,133 Memory elements having patterned electrodes and method of forming the same
A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes...
US-7,662,729 Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
Electronic apparatus and methods of forming the electronic apparatus include a conductive layer having a layer of ruthenium in contact with a lanthanide oxide...
US-7,662,719 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and...
A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method...
US-7,662,718 Trim process for critical dimension control for integrated circuits
Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of...
US-7,662,701 Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this...
US-7,662,693 Lanthanide dielectric with controlled interfaces
Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer...
US-7,662,658 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow...
US-7,662,649 Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing...
The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having...
US-7,662,648 Integrated circuit inspection system
Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a substrate....
US-7,662,299 Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and...
A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a...
US-7,660,708 S-matrix technique for circuit simulation
A methodology for combining two or more S-parameter blocks/matrices (each representing a circuit or network, or the interconnection between a circuit or network)...
US-7,660,187 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an...
US-7,660,172 Method and apparatus for synchronizing data from memory arrays
According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for...
US-7,660,158 Programming method to reduce gate coupling interference for non-volatile memory
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or...
US-7,660,144 High-performance one-transistor memory cell
A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential...
US-7,659,727 Multilayer wiring board and method for testing the same
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of...
US-7,659,630 Interconnect structures with interlayer dielectric
The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially...
US-7,659,612 Semiconductor components having encapsulated through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact....
US-7,659,560 Transistor structures
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill...
US-7,659,211 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect....
US-7,659,210 Nano-crystal etch process
A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing...
US-7,659,208 Method for forming high density patterns
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is...
US-7,659,205 Amorphous carbon-based non-volatile memory
A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A...
US-7,659,181 Sub-micron space liner and filler process
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,659,161 Methods of forming storage nodes for a DRAM array
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,659,152 Localized biasing for silicon on insulator structures
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned...
US-7,659,151 Flip chip with interposer, and methods of making same
A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller...
US-7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured....
US-7,657,802 Data compression read mode for memory testing
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first...
US-7,657,723 System and method for processor with predictive memory retrieval assist
A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the...
US-7,656,961 Method and apparatus for multi-user transmission
A method of transmitting data signals from at least two transmitting terminals to at least one receiving terminal with a spatial diversity antenna comprises...
US-7,656,768 Phase masks for use in holographic data storage
A spatial light modulator (SLM) having a phase mask that is provided as an internal component thereof. The phase mask can be provided as a multilevel surface of...
US-7,656,745 Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes...
US-7,656,740 Wordline voltage transfer apparatus, systems, and methods
The apparatus and systems comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a...
US-7,656,720 Power-off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
US-7,656,709 NAND step up voltage switching method
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a...
US-7,656,209 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,656,166 Multilayer wiring board and method for testing the same
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which...
US-7,656,049 CMOS device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-7,656,012 Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices...
A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The...
US-7,656,006 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor...
US-7,655,973 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-7,655,968 Semiconductor devices
A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during...
US-7,655,508 Overmolding encapsulation process and encapsulated article made therefrom
A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first...
US-7,655,507 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,655,500 Packaged microelectronic devices and methods for packaging microelectronic devices
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
US-7,655,387 Method to align mask patterns
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming...
US-7,655,384 Methods for reducing spherical aberration effects in photolithography
Methods to at least partially compensate for photoresist-induced spherical aberration that occurs during mask imaging used for photolithographic processing of...
US-7,655,095 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
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