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Patent # Description
US-7,709,399 Atomic layer deposition systems and methods including metal .beta.-diketiminate compounds
The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one .beta.-diketiminate ligand. Such...
US-7,709,390 Methods of isolating array features during pitch doubling processes and semiconductor device structures having...
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one...
US-7,709,345 Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth...
US-7,709,343 Use of a plasma source to form a layer during the formation of a semiconductor device
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
US-7,709,341 Methods of shaping vertical single crystal silicon walls and resulting structures
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon...
US-7,709,327 Methods of forming semiconductor-on-insulator substrates, and integrated circuitry
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,709,326 Methods of forming layers comprising epitaxial silicon
The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over...
US-7,709,289 Memory elements having patterned electrodes and method of forming the same
A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes...
US-7,709,279 Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events...
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD...
US-7,709,165 Image enhancement for multiple exposure beams
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by...
US-7,708,875 Noncontact localized electrochemical deposition of metal thin films
A method of selectively depositing metal features on a conductive surface of a substrate. An electrode assembly that includes a plurality of electrodes connected...
US-7,708,622 Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces
Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for...
US-7,707,718 Methods for assembling computers
Apparatuses and methods for preventing disengagement of electrical connectors in the assembly of computers. In one embodiment, a computer system includes a...
US-7,707,473 Integrated testing apparatus, systems, and methods
Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test...
US-7,707,467 Input/output compression and pin reduction in an integrated circuit
An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test...
US-7,707,368 Memory device trims
Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory...
US-7,706,647 Resistive heater for thermo optic device
Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing...
US-7,705,965 Backside lithography and backside immersion lithography
The present disclosure relates to formation of latent images in a radiation sensitive layer applied to a substrate that is transparent to or transmissive of...
US-7,705,963 Pupil improvement of incoherent imaging systems for enhanced CD linearity
A pattern generator may include an electromagnetic radiation source and an optical system. The electromagnetic radiation source may emit electromagnetic...
US-7,705,677 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,705,664 Current mirror circuit having drain-source voltage clamp
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output...
US-7,705,429 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,705,389 Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a...
US-7,705,383 Integrated circuitry for semiconductor memory
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor...
US-7,705,349 Test inserts and interconnects with electrostatic discharge structures
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD...
US-7,704,884 Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
US-7,704,849 Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-7,704,794 Method of forming a semiconductor device
A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than...
US-7,704,673 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-7,702,949 Use of non-volatile memory to perform rollback function
A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is...
US-7,701,788 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,701,782 Signal transfer apparatus and methods
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of...
US-7,701,780 Non-volatile memory cell healing
Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first...
US-7,701,776 Low power multiple bit sense amplifier
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers...
US-7,701,765 Non-volatile multilevel memory cell programming
The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower...
US-7,701,764 Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices
System and method for executing a global memory command in a multi-chip non-volatile memory device having a plurality of non-volatile memories. The global memory...
US-7,701,763 Leakage compensation during program and read operations
Methods of operating a memory and a memory are disclosed, such as an analog non-volatile memory device and process that reduces the effects of charge leakage...
US-7,701,762 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines...
US-7,701,760 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,701,741 Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell...
US-7,701,493 Imager row-wise noise correction
An imager having optically and electrically black reference pixels in each row of the imager's pixel array. Since the reference pixels of each row experience the...
US-7,701,462 Simple and robust color saturation adjustment for digital images
A method and system for adjusting saturation in digital images that operates as closely as possible to the long-, medium-, short-(LMS) cone spectral response...
US-7,701,443 Ergonomic computer mouse
An ergonomic computer mouse is provided. The mouse has at least one signaling device that is positioned to accommodate a user's fingers when they are in a...
US-7,701,272 Method and apparatus for output data synchronization with system clock
A circuit, delay-locked loop, memory device, system and method of synchronizing a clock are described. A circuit generally includes a delay line configured to...
US-7,701,184 Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Devices, reference voltage generators, systems and methods are disclosed, including an embodiment of a voltage regulator output transistor using a thin gate...
US-7,701,059 Low resistance metal silicide local interconnects and a method of making
A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of...
US-7,701,039 Semiconductor devices and in-process semiconductor devices having conductor filled vias
At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element...
US-7,700,989 Hafnium titanium oxide films
Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an...
US-7,700,497 Methods for fabricating residue-free contact openings
A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures...
US-7,700,485 Electro- and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
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