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| Patent # | Description |
|---|---|
| US-7,994,595 |
Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined... |
| US-7,994,566 |
Stacked non-volatile memory with silicon carbide-based amorphous silicon
finFETs A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a... |
| US-7,994,547 |
Semiconductor devices and assemblies including back side redistribution
layers in association with through... Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the... |
| US-7,994,491 |
PCRAM device with switching glass layer A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and... |
| US-7,994,464 |
Dual conversion gain gate and capacitor combination A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective... |
| US-7,993,988 |
Techniques for fabricating a non-planar transistor Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member).... |
| US-7,993,977 |
Method of forming molded standoff structures on integrated circuit devices A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a... |
| US-7,993,957 |
Phase change memory cell and manufacturing method thereof using
minitrenches A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin... |
| US-7,993,944 |
Microelectronic imagers with optical devices having integral reference
features and methods for manufacturing... Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed... |
| US-7,993,539 |
Methods of etching nanodots, methods of removing nanodots from substrates,
methods of fabricating integrated... Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated... |
| US-7,992,297 |
Method for forming a circuit board via structure for high speed signaling One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage... |
| US-7,992,060 |
Apparatus, methods, and system of NAND defect management Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a... |
| US-7,991,947 |
Multi-priority encoder A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder... |
| US-7,991,098 |
Method and apparatus for training the reference voltage level and data
sample timing in a receiver Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises... |
| US-7,990,802 |
Selective edge phase mixing Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and... |
| US-7,990,792 |
Hybrid sense amplifier and method, and memory device using same Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit.... |
| US-7,990,775 |
Methods of operating memory devices including different sets of logical
erase blocks Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second... |
| US-7,990,772 |
Memory device having improved programming operation Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and... |
| US-7,990,763 |
Memory with weighted multi-page read A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation.... |
| US-7,990,427 |
Method and apparatus for applying tonal correction to images A method and apparatus for applying tonal correction to images to obtain a more pleasing photographic image by redistributing low-key, mid-tone and high-key... |
| US-7,990,391 |
Memory system having multiple address allocation formats and method for
use thereof A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of... |
| US-7,990,163 |
Systems and methods for defect testing of externally accessible integrated
circuit interconnects Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads... |
| US-7,989,957 |
Self-aligned, integrated circuit contact Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer... |
| US-7,989,870 |
Use of dilute steam ambient for improvement of flash devices A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer,... |
| US-7,989,866 |
DRAM layout with vertical FETS and method of formation DRAM cell arrays having a cell area of about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The... |
| US-7,989,864 |
Methods for enhancing capacitors having roughened features to increase
charge-storage capacity Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from... |
| US-7,989,362 |
Hafnium lanthanide oxynitride films Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of... |
| US-7,989,360 |
Semiconductor processing methods, and methods for forming silicon dioxide Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate... |
| US-7,989,349 |
Methods of manufacturing nanotubes having controlled characteristics A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further,... |
| US-7,989,345 |
Methods of forming blind wafer interconnects, and related structures and
assemblies Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface... |
| US-7,989,340 |
Methods of forming CoSi.sub.2, methods of forming field effect
transistors, and methods of forming conductive... The invention included to methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts. In one... |
| US-7,989,336 |
Methods of forming a plurality of conductive lines in the fabrication of
integrated circuitry, methods of... A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a... |
| US-7,989,322 |
Methods of forming transistors Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for... |
| US-7,989,311 |
Strained semiconductor by full wafer bonding One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined... |
| US-7,989,307 |
Methods of forming isolated active areas, trenches, and conductive lines
in semiconductor structures and... Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography... |
| US-7,989,290 |
Methods for forming rhodium-based charge traps and apparatus including
rhodium-based charge traps Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic... |
| US-7,989,288 |
Transistor constructions and processing methods A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second... |
| US-7,989,285 |
Method of forming a film containing dysprosium oxide and hafnium oxide
using atomic layer deposition The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a... |
| US-7,989,251 |
Variable resistance memory device having reduced bottom contact area and
method of forming the same A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom... |
| US-7,989,022 |
Methods of processing substrates, electrostatic carriers for retaining
substrates for processing, and... A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to... |
| US-7,988,529 |
Methods and tools for controlling the removal of material from
microfeature workpieces Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method... |
| US-7,986,578 |
Low voltage sense amplifier and sensing method Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the... |
| US-7,986,576 |
Digit line equilibration using access devices at the edge of sub-arrays A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines... |
| US-7,986,563 |
NAND flash memory programming A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a... |
| US-7,986,555 |
Method for programming and erasing an NROM cell A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain... |
| US-7,986,553 |
Programming of a solid state memory utilizing analog communication of bit
patterns Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer... |
| US-7,986,549 |
Apparatus and method for refreshing or toggling a phase-change memory cell An apparatus and a method for refreshing or toggling a phase-change memory cell are described. The apparatus includes a voltage ramp element coupled to the... |
| US-7,986,363 |
High dynamic range imager with a rolling shutter A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the... |
| US-7,985,995 |
Zr-substituted BaTiO.sub.3 films The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO.sub.3), produces a reliable ferroelectric... |
| US-7,985,698 |
Methods of forming patterned photoresist layers over semiconductor
substrates This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is... |
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