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| Patent # | Description |
|---|---|
| US-7,859,050 |
Memory having a vertical access device Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a... |
| US-7,859,046 |
Ballistic direct injection NROM cell on strained silicon structures A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the... |
| US-7,859,036 |
Memory devices having electrodes comprising nanowires, systems including
same and methods of forming same Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form... |
| US-7,858,815 |
Systems and methods for forming tantalum oxide layers and tantalum
precursor compounds A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a... |
| US-7,858,535 |
Methods of reducing defect formation on silicon dioxide formed by atomic
layer deposition (ALD) processes and... Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished... |
| US-7,858,523 |
Unsymmetrical ligand sources, reduced symmetry metal-containing compounds,
and systems and methods including same The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In some... |
| US-7,858,518 |
Method for forming a selective contact and local interconnect in situ A process for the in situ formation of a selective contact and a local interconnect on a semiconductor substrate. The exposed semiconductor substrate regions of... |
| US-7,858,506 |
Diodes, and methods of forming diodes Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is... |
| US-7,858,486 |
Methods of forming a plurality of capacitors The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node... |
| US-7,858,471 |
Methods of fabricating an access transistor for an integrated circuit
device, methods of fabricating periphery... Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having... |
| US-7,858,468 |
Memory devices and formation methods A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant... |
| US-7,858,458 |
CMOS fabrication A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second... |
| US-7,858,420 |
Microelectronic imaging units and methods of manufacturing microelectronic
imaging units Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one... |
| US-7,857,982 |
Methods of etching features into substrates The invention includes methods of etching features into substrates. A plurality of hard mask layers is formed over material of a substrate to be etched. A... |
| US-7,857,646 |
Electrical testing apparatus having masked sockets and associated systems
and methods An apparatus for forming a temporary electrical connection with a microelectronic component and associated systems and methods are disclosed herein. Embodiments... |
| US-7,856,888 |
Fiber optic strain gage and carrier The current invention relates to optical gages designed to measure strain on the surface of a test specimen. The gages of this invention is designed to be... |
| US-7,855,931 |
Memory system and method using stacked memory device dice, and system
using the memory system A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is... |
| US-7,855,928 |
System and method for controlling timing of output signals The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an... |
| US-7,855,927 |
NAND system with a data write frequency greater than a
command-and-address-load frequency The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second... |
| US-7,855,922 |
Memory device bit line sensing system and method that compensates for bit
line resistance variations Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit... |
| US-7,855,913 |
Dynamically configurable MLC state assignment Memory devices and methods are disclosed, such as those facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device... |
| US-7,855,585 |
Local coarse delay units One delay locked loop circuit embodiment includes a delay line system configured to generate a clock output signal by adding a delay line system time delay to a... |
| US-7,855,462 |
Packaged semiconductor assemblies and methods for manufacturing such
assemblies Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of... |
| US-7,855,454 |
Semiconductor device structures including nickel plated aluminum, copper,
and tungsten structures A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate... |
| US-7,855,341 |
Methods and apparatus for a flexible circuit interposer A substrate having a bending region and conductive paths formed therethrough is provided. In one embodiment, conductive paths are formed from a first region on... |
| US-7,855,154 |
Methods of forming intermediate semiconductor device structures using
spin-on, photopatternable, interlayer... A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously... |
| US-7,855,148 |
Methods of isolating array features during pitch doubling processes and
semiconductor device structures having... Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one... |
| US-7,855,140 |
Method of forming vias in semiconductor substrates and resulting
structures Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a... |
| US-7,855,085 |
System and method for reducing shorting in memory cells An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce... |
| US-7,854,644 |
Systems and methods for removing microfeature workpiece surface defects Systems and methods for removing microfeature workpiece surface defects are disclosed. A method for processing a microfeature workpiece in accordance with one... |
| US-7,853,841 |
Memory cell programming Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One... |
| US-7,853,725 |
USB device communication apparatus, systems, and methods Methods, systems and apparatus may operate to send and receive universal serial bus (USB) control endpoint standard device requests with embedded functional... |
| US-7,852,681 |
Non-volatile one time programmable memory A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further... |
| US-7,852,671 |
Data path for multi-level cell memory, methods for storing and methods for
utilizing a memory array Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide... |
| US-7,852,668 |
Semiconductor magnetic memory integrating a magnetic tunneling junction
above a floating-gate memory cell A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating... |
| US-7,852,658 |
Phase change memory cell with constriction structure Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the... |
| US-7,852,385 |
Imager row-wise noise correction An imager having optically and electrically black reference pixels in each row of the imager's pixel array. Since the reference pixels of each row experience the... |
| US-7,852,112 |
On-die system and method for controlling termination impedance of memory
device data bus terminals A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a... |
| US-7,851,907 |
Semiconductor integrated circuit package having electrically disconnected
solder balls for mounting Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are... |
| US-7,851,869 |
Semiconductor constructions The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material... |
| US-7,851,850 |
Band engineered nano-crystal non-volatile memory device utilizing enhanced
gate injection Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal... |
| US-7,851,827 |
Back-side trapped non-volatile memory device Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with... |
| US-7,851,798 |
Method and apparatus for dark current and blooming suppression in 4T CMOS
imager pixel A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a... |
| US-7,851,309 |
Selective epitaxy vertical integrated circuit components and methods Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are... |
| US-7,851,307 |
Method of forming complex oxide nanodots for a charge trap Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is... |
| US-7,851,301 |
Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride... |
| US-7,851,292 |
Methods of forming and programming floating-gate memory cells having
carbon nanotubes Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into... |
| US-7,851,266 |
Microelectronic device wafers including an in-situ molded adhesive, molds
for in-situ molding adhesives on... A microelectronic device wafer includes an adhesive molded in-situ on the wafer. Adhesives and wafers are positioned in molds and a method that includes drawing... |
| US-7,849,276 |
Host memory interface for a parallel processor A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory... |
| US-7,848,569 |
Method and apparatus providing automatic color balancing for digital
imaging systems Pixels from an image are sampled for gray world statistics. To avoid the effect of saturated regions, the pixels are pruned. If a predetermined percentage of the... |
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