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Dual panel pixel readout in an imager
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual...
Animation packager for an on-line book
A system for creating an on-line book with an animated cover. The system includes an animation program for inserting an animation sequence at the beginning of an...
Pusher assemblies for use in microfeature device testing, systems with
pusher assemblies, and methods for using...
Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment...
Microelectronic component assemblies and microelectronic component lead
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
Process for fabricating films of uniform properties on semiconductor
A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying...
Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns....
Memory transistor and methods
A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At...
Methods of forming programmable memory devices
The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed...
Methods and systems for pattern generation based on multiple forms of
In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write...
Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
Delayed activation of selected wordlines in memory
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation...
Assemblies for plasma-enhanced treatment of substrates
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
Raised photodiode sensor to increase fill factor and quantum efficiency in
An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised...
Compliant spring contact structures
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a...
Systems and methods for forming metal oxides using metal diketonates
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
Methods of forming semiconductor constructions, and methods of recessing
materials within openings
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.8. The recessed...
Vias having varying diameters and fills for use with a semiconductor
device and methods of forming...
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second...
Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
Methods of forming DRAM arrays
Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include...
Methods for attaching microfeature dies to external devices
Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other...
System and method for heating, cooling and heat cycling on microfluidic
An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and...
Phase shift mask with two-phase clear feature
Systems and methods are provided for use in photolithography. In one embodiment, a reticle is provided that comprises a phase shift and transmission control...
Systems for depositing material onto workpieces in reaction chambers and
methods for removing byproducts from...
Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one...
Systems, methods, and computer-readable media for adjusting layout
database hierarchies for more efficient...
Systems and methods are disclosed for organizing layout data. A layout database is analyzed to determine a statistical distribution of cells within the layout...
Graphics engine for high precision lithography
The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability...
Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
Digital exposure circuit for an image sensor
Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the...
Method of output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
On-die system and method for controlling termination impedance of memory
device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a...
Wafer level pre-packaged flip chip systems
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment,...
Self-aligned, integrated circuit contact
Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer...
Microelectronic imagers having front side contacts
Microelectronic imager assemblies with front side contacts and methods for fabricating such microelectronic imager assemblies are disclosed herein. In one...
Memory cell storage node length
Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first...
Method for automated testing of the modulation transfer function in image
A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the...
Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
Recessed access device for a memory
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a...
Frame structure and semiconductor attach process for use therewith for
fabrication of image sensor packages and...
A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture...
Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
Apparatus for attaching solder balls to BGA package utilizing a tool to
pick and dip the solder ball in flux
A method of attaching solder balls to a BGA package using a ball pickup tool is disclosed. An array of solder balls is formed on a first substrate for...
Memory hub with internal cache and/or memory access prediction
A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory ("SDRAM") devices. The memory hub...
Memory device controller
A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core...
Device and method for configuring a cache tag in accordance with burst
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not...
Method and system for selecting compatible processors to add to a
A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program...
Memory device having conditioning output data
Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing...
Clock generating circuit with multiple modes of operation
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock...
NAND string with a redundant memory cell
The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled...
Process for erasing chalcogenide variable resistance memory bits
A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate...
Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second...
Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via,...
Apparatus for molding a semiconductor die package with enhanced thermal
A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back...