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| Patent # | Description |
|---|---|
| US-7,771,537 |
Methods and systems for controlling temperature during microfeature
workpiece processing, E.G. CVD deposition The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in... |
| US-7,771,220 |
Electrical connecting apparatus An embodiment of an electrical connecting apparatus comprises an electrical insulating plate, an elastic plate made of an electrical insulating material arranged... |
| US-7,771,115 |
Temperature sensor circuit, device, system, and method A sensor, device, system and method for sensing temperature includes a pull up circuit coupled to a pull down circuit for generating a variable pull up output... |
| US-7,770,079 |
Error scanning in flash memory Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is... |
| US-7,769,286 |
Method and apparatus of determining the best focus position of a lens A method and apparatus for accurately auto focusing a lens of an imaging device. An imaged scene is split into an array of zones. The minimum and maximum... |
| US-7,768,868 |
Digital filters for semiconductor devices A memory device that, in certain embodiments, includes a memory element and a digital filter. The digital filter may include a counter and a divider, where the... |
| US-7,768,861 |
Software refreshed memory device and method A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells... |
| US-7,768,846 |
Individual I/O modulation in memory devices A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are... |
| US-7,768,839 |
Memory read methods, apparatus, and systems Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to... |
| US-7,768,838 |
Operating memory cells Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a... |
| US-7,768,835 |
Non-volatile memory erase verify A memory device having memory cells fabricated in a substrate well is described. The memory device includes control circuitry to perform an erase operation on... |
| US-7,768,832 |
Analog read and write paths in a solid state memory device A memory array in a memory device is coupled to an analog I/O data interface that enables analog voltage levels to be written to the memory array. The I/O... |
| US-7,768,812 |
Memory cells, memory cell programming methods, memory cell reading
methods, memory cell operating methods, and... Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In... |
| US-7,768,562 |
Method, apparatus and system providing imager vertical binning and scaling
using column parallel sigma-delta... A method, apparatus and system are disclosed for digitizing a plurality of analog pixel signals of a pixel array in a manner which produces a digital signal... |
| US-7,768,096 |
System for fabricating semiconductor components with conductive
interconnects A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching... |
| US-7,768,073 |
Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a... |
| US-7,768,062 |
Combined volatile and non-volatile memory device with graded composition
insulator stack A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The... |
| US-7,768,058 |
NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is... |
| US-7,768,051 |
DRAM including a vertical surround gate transistor DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect... |
| US-7,768,049 |
Polymer-based ferroelectric memory Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster... |
| US-7,768,047 |
Imager element, device and system with recessed transfer gate An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer... |
| US-7,768,040 |
Imager device with electric connections to electrical device An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the... |
| US-7,768,036 |
Integrated circuitry This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer... |
| US-7,767,913 |
Electronic devices including conductive vias having two or more conductive
elements for providing electrical... Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting... |
| US-7,767,557 |
Chilled wafer dicing A method for dicing a wafer is disclosed. One illustrative method includes forming a layer of frozen material above a plurality of integrated circuit dies on a... |
| US-7,767,544 |
Semiconductor fabrication method and system Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes... |
| US-7,767,525 |
Methods of forming vertical transistor structures The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical... |
| US-7,767,514 |
Methods of implanting dopant into channel regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger... |
| US-7,767,365 |
Methods for forming and cleaning photolithography reticles A method for removing impurities (e.g., atomic sulfur) from a reticle for use in photolithography is provided. In one embodiment, a reticle (or photomask)... |
| US-7,767,363 |
Methods for photo-processing photo-imageable material The invention includes methods for photo-processing photo-imageable material. Locations of the photo-imageable material where flare hot spots are expected to... |
| US-7,767,129 |
Imprint templates for imprint lithography, and methods of patterning a
plurality of substrates The invention comprises methods of patterning a plurality of substrates, and imprint templates used in imprint lithography. In one implementation, a method of... |
| US-7,765,426 |
Emerging bad block detection Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques... |
| US-7,765,424 |
System and method for injecting phase jitter into integrated circuit test
signals A memory test system injects phase jitter in memory command, address and write data signals in respective pin groups. A phase interpolator receiving a clock... |
| US-7,764,567 |
Word line driver circuitry and methods for using the same Word line driver circuitry for selectively, charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology,... |
| US-7,764,563 |
Adjustable voltage regulator for providing a regulated output voltage Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator... |
| US-7,764,558 |
Hybrid sense amplifier and method, and memory device using same Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit.... |
| US-7,764,554 |
I/O circuit with phase mixer for slew rate control An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state... |
| US-7,764,073 |
Electrical connecting apparatus The electrical connecting apparatus comprises: a wiring base plate having a first surface provided with a plurality of first conductive portions; a probe base... |
| US-7,763,933 |
Transistor constructions and processing methods A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second... |
| US-7,763,548 |
Microfeature workpiece processing system for, e.g., semiconductor wafer
analysis The present disclosure suggests apparatus and methods that can be used to chemically process microfeature workpieces, e.g., semiconductor wafers. One... |
| US-7,763,499 |
CMOS front end process compatible low stress light shield An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding... |
| US-7,763,497 |
Structure and method for forming a capacitively coupled chip-to-chip
signaling interface A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first... |
| US-7,763,453 |
Microfluidic mixing and analytic apparatus Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles... |
| US-7,763,327 |
Methods using ozone for CVD deposited films A CVD ozone (O.sub.3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and... |
| US-7,760,582 |
Apparatus for memory device wordline A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a... |
| US-7,760,533 |
Systems, methods and devices for arbitrating die stack position in a
multi-bit stack device Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked... |
| US-7,760,532 |
Multi-bank memory A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another... |
| US-7,760,329 |
Optimized optical lithography illumination source for use during the
manufacture of a semiconductor device A method and structure for optimizing an optical lithography illumination source may include a shaped diffractive optical element (DOE) interposed between the... |
| US-7,760,019 |
Adaptive operational transconductance amplifier load compensation A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The... |
| US-7,759,800 |
Microelectronics devices, having vias, and packaged microelectronic
devices having vias Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and... |
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