Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: micron
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,795,093 |
Front-end processing of nickel plated bond pads A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an... |
| US-7,794,787 |
Methods of depositing materials over substrates, and methods of forming
layers over substrates The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is... |
| US-7,793,075 |
Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU... |
| US-7,791,952 |
Memory device architectures and operation Non-volatile memory devices logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks... |
| US-7,791,941 |
Non-volatile SRAM cell Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring... |
| US-7,791,612 |
Fully associative texture cache having content addressable memory and
method for use thereof A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data... |
| US-7,791,388 |
Duty cycle error calculation circuit for a clock generator having a delay
locked loop and duty cycle correction... A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal.... |
| US-7,791,364 |
Electronic device probe card with improved probe grouping The probe card includes a plurality of probes arranged on one surface side of a board. These probes belonging to any one of a first probe group including a... |
| US-7,791,207 |
Pass through via technology for use during the manufacture of a
semiconductor device Via structures are described which pass through a semiconductor substrate assembly such as a semiconductor die or wafer and allows for two different types of... |
| US-7,791,205 |
Interposers for semiconductor die packages with standard ball grill array
footprint Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to... |
| US-7,791,203 |
Interconnects for packaged semiconductor devices and methods for
manufacturing such devices Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a... |
| US-7,791,184 |
Image sensor packages and frame structure thereof A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image... |
| US-7,791,143 |
Semiconductor constructions In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anisotropically... |
| US-7,791,116 |
CMOS imager having a nitride dielectric An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen... |
| US-7,791,071 |
Profiling solid state samples Methods and apparatus may operate to position a sample, including an imager lens surface, within a processing chamber. Further activities may include creating a... |
| US-7,791,058 |
Enhanced memory density resistance variable memory cells, arrays, devices
and systems including the same, and... A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable... |
| US-7,791,055 |
Electron induced chemical etching/deposition for enhanced detection of
surface defects A method of imaging and identifying defects and contamination on the surface of an integrated circuit is described. The method may be used on areas smaller than... |
| US-7,790,632 |
Methods of forming a phosphorus doped silicon dioxide-comprising layer This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of... |
| US-7,790,603 |
Integrated circuit insulators and related methods A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for... |
| US-7,790,544 |
Method of fabricating different gate oxides for different transistors in
an integrated circuit An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication... |
| US-7,790,531 |
Methods for isolating portions of a loop of pitch-multiplied material and
related structures Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is... |
| US-7,790,529 |
Methods of forming memory arrays and semiconductor constructions Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active... |
| US-7,790,360 |
Methods of forming multiple lines Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as... |
| US-7,790,338 |
Optical compensation devices, systems, and methods Photolithographic apparatus, systems, and methods that make use of optical compensation devices are disclosed. In various embodiments, an imaging mask includes... |
| US-7,789,319 |
System and method for recirculating fluid supply for an injector for a
semiconductor fabrication chamber One embodiment of the present subject matter includes a system which includes a tank, a conduit is adapted to carry a recirculating supply of fluid from the tank... |
| US-7,788,451 |
Apparatus and method for data bypass for a bi-directional data bus in a
hub-based memory sub-system A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and... |
| US-7,787,310 |
Circuits, devices, systems, and methods of operation for capturing data
signals Embodiments of the invention are described for driving data onto a data bus. The embodiments include a data driver circuit having a data capture circuit coupled... |
| US-7,787,307 |
Memory cell shift estimation method and apparatus Memory devices and methods are disclosed, such as those facilitating interpolation methods for reference memory cells based on their reference state and/or... |
| US-7,787,282 |
Sensing resistance variable memory The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a... |
| US-7,787,174 |
Pattern generator The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical... |
| US-7,786,803 |
Operational transconductance amplifier (OTA) Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include... |
| US-7,786,605 |
Stacked semiconductor components with through wire interconnects (TWI) A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact.... |
| US-7,786,522 |
Method for forming memory cell and device A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to... |
| US-7,786,516 |
Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of... |
| US-7,786,016 |
Methods of uniformly removing silicon oxide and a method of removing a
sacrificial oxide A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one... |
| US-7,785,998 |
Methods of forming dispersions of nanoparticles, and methods of forming
flash memory cells Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the... |
| US-7,785,978 |
Method of forming memory cell using gas cluster ion beams A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the... |
| US-7,785,976 |
Method of forming a memory device incorporating a resistance-variable
chalcogenide element A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and... |
| US-7,785,962 |
Methods of forming a plurality of capacitors A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises... |
| US-7,785,961 |
Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for... |
| US-7,783,934 |
Program failure recovery A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory... |
| US-7,782,677 |
NAND memory device column charging Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on... |
| US-7,782,674 |
Sensing of memory cells in NAND flash An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells... |
| US-7,781,877 |
Packaged integrated circuit devices with through-body conductive vias, and
methods of making same A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at... |
| US-7,781,875 |
Techniques for packaging multiple device components Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a... |
| US-7,781,868 |
Semiconductor components having through interconnects and backside
redistribution conductors A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality... |
| US-7,781,860 |
Semiconductor constructions, and electronic systems The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can... |
| US-7,781,818 |
Semiconductor constructions containing tubular capacitor storage nodes,
and retaining structures along portions... The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention... |
| US-7,779,212 |
Method and apparatus for sending data from multiple sources over a
communications bus In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives... |
| US-7,778,812 |
Selecting data to verify in hardware device model simulation test
generation Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.