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| Patent # | Description |
|---|---|
| US-7,700,480 |
Methods of titanium deposition Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to... |
| US-7,700,478 |
Intermediate anneal for metal deposition The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process... |
| US-7,700,469 |
Methods of forming semiconductor constructions Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second... |
| US-7,700,441 |
Methods of forming field effect transistors, methods of forming field
effect transistor gates, methods of... The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry... |
| US-7,700,436 |
Method for forming a microelectronic structure having a conductive
material and a fill material with a hardness... A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the... |
| US-7,700,422 |
Methods of forming memory arrays for increased bit density A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,... |
| US-7,700,406 |
Methods of assembling integrated circuit packages Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of... |
| US-7,699,998 |
Method of substantially uniformly etching non-homogeneous substrates A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including... |
| US-7,699,932 |
Reactors, systems and methods for depositing thin films onto microfeature
workpieces A reactor, system including reactors, and methods for depositing thin films on microfeature workpieces comprising a reaction vessel having a chamber, a gas... |
| US-7,699,630 |
Memory module having a cover pivotally coupled thereto A storage device has a memory module and a cover pivotally coupled to a housing of the memory module. In one such storage device, the memory module and cover can... |
| US-7,698,499 |
Method and apparatus for address FIFO for high-bandwidth command/address
busses in digital storage system A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change... |
| US-7,697,357 |
Negative voltage driving for the digit line isolation gates A system and method to reduce standby leakage current in the event of row-to-column shorts in a memory chip or in an electronic device having memory or data... |
| US-7,697,335 |
Multiple select gate architecture Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing... |
| US-7,697,328 |
Split gate flash memory cell with ballistic injection A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of... |
| US-7,697,324 |
Non-volatile memory device and method having bit-state assignments
selected to minimize signal coupling A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the... |
| US-7,696,778 |
Systems and methods for detecting terminal state and setting output driver
impedance Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to... |
| US-7,696,624 |
Nucleation method for atomic layer deposition of cobalt on bare silicon
during the formation of a semiconductor... A method used to form a cobalt metal layer on a silicon surface using an atomic layer deposition (ALD) process comprises a treatment of the silicon surface prior... |
| US-7,696,579 |
Formation of standard voltage threshold and low voltage threshold MOSFET
devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first... |
| US-7,696,568 |
Semiconductor device having reduced sub-threshold leakage A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed... |
| US-7,696,567 |
Semiconductor memory device A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical... |
| US-7,696,557 |
Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory
array architecture, fabrication and... Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column... |
| US-7,696,545 |
Skimmed charge capture and charge packet removal for increased effective
pixel photosensor full well capacity An imaging device having pixels that store charge from a photosensor under at least one storage gate during a sampling period. A driver used to operate the at... |
| US-7,696,101 |
Process for increasing feature density during the manufacture of a
semiconductor device A method used during the manufacture of a semiconductor device comprises the formation of a first patterned layer having individual features of a first density.... |
| US-7,696,077 |
Bottom electrode contacts for semiconductor devices and methods of forming
same Bottom electrode contact structures for a semiconductor assembly and a method for forming same are described. An exemplary semiconductor device comprises... |
| US-7,696,056 |
Methods of forming capacitors A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across... |
| US-7,696,042 |
Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride... |
| US-7,696,011 |
Methods for applying front side and edge protection material to electronic
devices at the wafer level, devices... Methods for applying a dielectric protective layer to a wafer in wafer-level chip-scale package manufacture are disclosed. A flowable dielectric protective... |
| US-7,696,003 |
Microelectronic component assemblies with recessed wire bonds and methods
of making same The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one... |
| US-7,695,994 |
Material sidewall deposition method A method of forming a layer of material on a sidewall of a via with good thickness control. The method involves forming a layer of material with a conventional... |
| US-7,694,202 |
Providing memory test patterns for DLL calibration A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial... |
| US-7,692,996 |
Method, system, and apparatus for voltage sensing and reporting A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is... |
| US-7,692,984 |
System and method for initiating a bad block disable process in a
non-volatile memory A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid... |
| US-7,692,975 |
System and method for mitigating reverse bias leakage The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of... |
| US-7,692,971 |
Non-volatile multilevel memory cell programming Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method... |
| US-7,692,931 |
Microelectronic packages with leadframes, including leadframes configured
for stacked die packages, and... Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in... |
| US-7,692,705 |
Active pixel sensor with a diagonal active area An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent... |
| US-7,692,463 |
Devices and methods for controlling a slew rate of a signal line In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were... |
| US-7,692,437 |
Systems and methods for testing packaged microelectronic devices Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a... |
| US-7,692,210 |
Intermeshed guard bands for multiple voltage supply structures on an
integrated circuit, and methods of making same The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of... |
| US-7,692,177 |
Resistance variable memory element and its method of formation A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin... |
| US-7,691,726 |
Reduced footprint packaged microelectronic components and methods for
manufacturing such microelectronic components The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and ... |
| US-7,691,722 |
Isolation trench fill using oxide liner and nitride etch back technique
with dual trench depth capability An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such... |
| US-7,691,683 |
Electrode structures and method to form electrode structures that minimize
electrode work function variation Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an... |
| US-7,691,682 |
Build-up-package for integrated circuit devices, and methods of making
same A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a... |
| US-7,691,680 |
Method of fabricating microelectronic component assemblies employing lead
frames having reduced-thickness inner... The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one... |
| US-7,689,879 |
System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors,... |
| US-7,688,653 |
Method and system for improved efficiency of synchronous mirror delays and
delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and... |
| US-7,688,635 |
Current sensing for Flash A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing... |
| US-7,688,630 |
Programming memory devices A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether... |
| US-7,688,378 |
Imager method and apparatus employing photonic crystals An image sensor and a method of forming an image sensor. The image sensor includes an array of pixel cells at a surface of a substrate. Each pixel cell has a... |
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